Datasheet AD5308 Datasheet (Analog Devices)

2.5 V to 5.5 V Octal Voltage Output

8-/10-/12-Bit DACs in 16-Lead TSSOP

FEATURES
AD5308: 8 Buffered 8-Bit DACs in 16-Lead TSSOP

A Version: ⴞ1 LSB INL, B Version: ⴞ0.75 LSB INL

AD5318: 8 Buffered 10-Bit DACs in 16-Lead TSSOP

A Version: ⴞ4 LSB INL, B Version: ⴞ3 LSB INL

AD5328: 8 Buffered 12-Bit DACs in 16-Lead TSSOP

A Version: ⴞ16 LSB INL, B Version: ⴞ12 LSB INL
Low Power Operation: 0.7 mA @ 3 V
Guaranteed Monotonic by Design over All Codes
Power-Down to 120 nA @ 3 V, 400 nA @ 5 V
Double-Buffered Input Logic
Buffered/Unbuffered/V
Output Range: 0 V to V

Reference Input Options

DD

or 0 V to 2 V

REF

REF

Power-On Reset to 0 V
Programmability

Individual Channel Power-Down

Simultaneous Update of Outputs (LDAC)
Low Power, SPI

®

, QSPI™, MICROWIRE™, and DSP

Compatible 3-Wire Serial Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Optical Networking
Automatic Test Equipment

FUNCTIONAL BLOCK DIAGRAM

V

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

SCLK

SYNC

DIN

LDAC

INTERFACE

LOGIC

AD5308/AD5318/AD5328

Mobile Communications
Programmable Attenuators
Industrial Process Control

GENERAL DESCRIPTION

The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typ at 3 V.
Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5308/AD5318/
AD5328 use a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard
SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the eight DACs are derived from two reference
pins (one per DAC quad). These reference inputs can be
configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the DAC
outputs power up to 0 V and remain there until a valid write to
the device takes place. The outputs of all DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump­tion of the devices to 400 nA at 5 V (120 nA at 3 V). The eight
channels of the DAC may be powered down individually.

All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.

V

ABCD

REF

V

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

STRING
DAC A

STRING
DAC B

STRING
DAC C

STRING
DAC D

STRING
DAC E

STRING
DAC F

STRING
DAC G

STRING
DAC H

DD

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

BUFFER

GAIN-SELECT

LOGIC

A

V

OUT

B

V

OUT

C

V

OUT

D

V

OUT

E

V

OUT

V

F

OUT

G

V

OUT

H

V

OUT

*

POWER-ON

RESET

LDAC

*Protected by U.S.Patent No. 5,969,657; other patents pending.

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

GAIN-SELECT

LOGIC

V

DD

EFGH

V

REF

POWER-DOWN

LOGIC

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5308/AD5318/AD5328–SPECIFICATIONS

GND; C

= 200 pF to GND; all specifications T

L

Parameter

DC PERFORMANCE

1

3, 4

Min Typ Max Min Typ Max Unit Conditions/Comments

to T

MIN

A Version

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5308

Resolution 8 8 Bits
Relative Accuracy ±0.15 ±1 ±0.15 ±0.75 LSB
Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed Monotonic by Design over All Codes

AD5318

Resolution 10 10 Bits
Relative Accuracy ±0.5 ±4 ±0.5 ±3 LSB
Differential Nonlinearity ±0.05 ±0.50 ±0.05 ±0.50 LSB Guaranteed Monotonic by Design over All Codes

AD5328

Resolution 12 12 Bits
Relative Accuracy ±2 ±16 ±2 ±12 LSB

Differential Nonlinearity ±0.2 ±1.0 ±0.2 ±1.0 LSB Guaranteed Monotonic by Design over All Codes
Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR VDD = 4.5 V, Gain = +2. See Figures 2 and 3.
Lower Deadband

Upper Deadband

Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1.0 VDD1.0 V

REF

V

Input Impedance (R

REF

5

5

6

6

6

6

6

) >10.0 >10.0 MΩ Buffered Reference Mode and Power-Down Mode

DAC

10 60 10 60 mV See Figure 2. Lower deadband exists only if offset

error is negative.

10 60 10 60 mV See Figure 3. Upper deadband exists only if V

VDD and offset plus gain error is positive.

–12 –12 ppm of FSR/°C
–5 –5 ppm of FSR/°C
–60 –60 dB VDD = ± 10%
200 200 µVR

V Buffered Reference Mode

0.25 VDD0.25 V

DD

V Unbuffered Reference Mode

DD

37.0 45.0 37.0 45.0 kΩ Unbuffered Reference Mode. 0 V to V

18.0 22.0 18.0 22.0 kΩ Unbuffered Reference Mode. 0 V to 2 V

= 2 kΩ to GND or V

L

Output Range.

Output Range.

DD

REF

REF

Reference Feedthrough –70.0 –70.0 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75.0 –75.0 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

6

7

7

0.001 0.001 V This is a measure of the minimum and maximum
VDD – 0.001 VDD – 0.001 V drive capability of the output amplifier.

DC Output Impedance 0.5 0.5 Ω
Short Circuit Current 25.0 25.0 mA VDD = 5 V

16.0 16.0 mA VDD = 3 V

Power-Up Time 2.5 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V.

5.0 5.0 µs Coming Out of Power-Down Mode. VDD = 3 V.

LOGIC INPUTS

6

Input Current ±1 ±1 µA
VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.8 0.8 V VDD = 3 V ± 10%

0.7 0.7 V VDD = 2.5 V

VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V; TTL and CMOS

Compatible

Pin Capacitance 3.0 3.0 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

8

2.5 5.5 2.5 5.5 V
VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.0 1.8 1.0 1.8 mA All DACs in Unbuffered Mode. In Buffered mode,
VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA extra current is typically x µA per DAC; x = (5 µA

IDD (Power-Down Mode)

9

+ V
VIH = VDD and VIL = GND

REF/RDAC

)/4.

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 µA
VDD = 2.5 V to 3.6 V 0.12 1 0.12 1 µA

NOTES

1

See the Terminology section.

2

Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
must be positive.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

= VDD and offset plus gain error

REF

Specifications subject to change without notice.

REF

=

REV. B–2–

AD5308/AD5318/AD5328

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

1

AC CHARACTERISTICS

Parameter

2

otherwise noted.)

A, B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

MAX

, unless

AD5308 6 8 µs 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5318 7 9 µs 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5328 8 10 µs 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Slew Rate 0.7 V/µs
Major-Code Change Glitch Energy 12 nV-s 1 LSB Change around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range (A, B Version): –40°C to +105°C; typical at +25°C.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

1, 2, 3

= 2 V ± 0.1 V p-p. Unbuffered Mode.

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz.

REF

A, B Version

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

NOTES

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 2 and 3.

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK Falling Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
0 ns min SCLK Falling Edge to LDAC Falling Edge

MIN

, T

MAX

Unit Conditions/Comments

t

1

REV. B

SCLK

t

8

SYNC

DIN DB15

1

LDAC

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE

2

SYNCHRONOUS LDAC UPDATE MODE

t

t

t

4

t

6

t

5

3

2

t

7

DB0

t

9

t

11

t

10

Figure 1. Serial Interface Timing Diagram

–3–

AD5308/AD5318/AD5328

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

OUT

A–V

D to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A, B Version) . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

J MAX

1, 2

+ 0.3 V

DD

+ 0.3 V

DD

) . . . . . . . . . . . . . . . . . . . 150°C

16-Lead TSSOP

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

J MAX

– TA)/␪

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4°C/W

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5308ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5308BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5318BRUZ-REEL7* –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328ARU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16
AD5328BRU-REEL7 –40°C to +105°CThin Shrink Small Outline Package (TSSOP) RU-16

*Z = Pb-free part.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5308/AD5318/AD5328 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. B–4–

PIN CONFIGURATION

AD5308/AD5318/AD5328

LDAC

1

SYNC

2

AD5308/

V

3

AD5318/

DD

A

4

B

5

(Not to Scale)

C

6

D

7

8

AD5328

TOP VIEW

V

OUT

V

OUT

V

OUT

V

OUT

V

ABCD

REF

SCLK

16

DIN

15

GND

14

H

V

13

OUT

G

V

12

OUT

F

V

11

OUT

V

E

10

OUT

V

EFGH

9

REF

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 LDAC This active low-control input transfers the contents of the input registers to their respective DAC registers.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low.

2 SYNC Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

3V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4V

5V

6V

7V

8V

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

CBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

DBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

ABCD Reference Input Pin for DACs A, B, C, and D. It may be configured as a buffered, unbuffered, or V

REF

DD

input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range

9V

EFGH Reference Input Pin for DACs E, F, G, and H. It may be configured as a buffered, unbuffered, or V

REF

from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

DD

input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

10 V

11 V

12 V

13 V

from 0.25 V to V

EBuffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

FBuffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

OUT

GBuffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

OUT

HBuffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

OUT

14 GND Ground Reference Point for All Circuitry on the Part.

15 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

16 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after
each write cycle.

REV. B

–5–

AD5308/AD5318/AD5328

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier (see Figures 2 and 3). It can be negative or positive,
and is expressed in mV.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V

OUT

to a change in VDD for full-scale output of the DAC. It is mea­sured in dB. V

DC Crosstalk

is held at 2 V and VDD is varied ±10%.

REF

This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in µV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC out­put to the reference input when the DAC output is not being
updated (i.e., LDAC is high). It is expressed in dB.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to (SYNC
held high). It is specified in nV-s and is measured with a full­scale change on the digital input pins, i.e., from all 0s to all 1s
and vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.

REV. B–6–

OUTPUT

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

DAC CODE

GAIN ERROR

AND

OFFSET ERROR

ACTUAL

IDEAL

UPPER
DEADBAND
CODES

FULL SCALE

VOLTAGE

GAIN ERROR

AND

OFFSET ERROR

AD5308/AD5318/AD5328

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

LOWER

DEADBAND

CODES

DAC CODE

ACTUAL

IDEAL

Figure 2. Transfer Function with Negative Offset
(V

= VDD)

REF

Figure 3. Transfer Function with Positive Offset

REV. B

–7–

AD5308/AD5318/AD5328–Typical Performance Characteristics

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR (LSB)

–0.5

–1.0

050 250100 150 200

CODE

TPC 1. AD5308 Typical INL Plot

0.3
TA = 25ⴗC

= 5V

V

DD

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

3

TA = 25ⴗC
V

= 5V

DD

2

1

0

–1

INL ERROR (LSB)

–2

–3

0 200 1000

400 600 800

CODE

TPC 2. AD5318 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

12

TA = 25ⴗC

= 5V

V

DD

8

4

0

–4

INL ERROR (LSB)

–8

–12

0 40001000 2000 3000

CODE

TPC 3. AD5328 Typical INL Plot

1.0
TA = 25ⴗC

= 5V

V

DD

0.5

0

DNL ERROR (LSB)

–0.5

–0.3

050 250100 150 200

CODE

TPC 4. AD5308 Typical DNL Plot

0.50

VDD = 5V

= 25ⴗC

T

A

0.25

0

ERROR (LSB)

–0.25

–0.50

01 5234

MAX INL

MIN DNL

MIN INL

V

REF

MAX DNL

(V)

TPC 7. AD5308 INL and DNL
Error vs. V

REF

–0.6

2000

CODE

600400

800 1000

TPC 5. AD5318 Typical DNL Plot

0.5

VDD = 5V

0.4

0.3

0.2

0.1

–0.1

ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

= 3V

V

REF

0

ⴚ40 0 40

MAX INL

MAX DNL

TEMPERATURE (ⴰC)

MIN DNL

MIN INL

80 120

TPC 8. AD5308 INL Error and
DNL Error vs. Temperature

–1.0

10000

2000

CODE

3000 4000

TPC 6. AD5328 Typical DNL Plot

1.0

VDD = 5V

= 2V

V

REF

0.5

GAIN ERROR

0

ERROR (% FSR)

–0.5

–1.0

ⴚ40 0 40

OFFSET ERROR

80 120

TEMPERATURE (ⴰC)

TPC 9. AD5308 Offset Error and
Gain Error vs. Temperature

REV. B–8–

AD5308/AD5318/AD5328

0.2
TA = 25ⴗC

0.1

–0.1

–0.2

–0.3

ERROR (% FSR)

–0.4

–0.5

–0.6

= 2V

V

REF

0

01 3

GAIN ERROR

OFFSET ERROR

25

VDD (V)

TPC 10. Offset Error and
Gain Error vs. V

1.3
T

= 25ⴗC

A

1.2

V

1.1

1.0

(mA)

DD

I

0.9

0.8

0.7

0.6

2.0

REF

V

= 2V, GAIN = +1, UNBUFFERED

REF

= V

V

REF

2.5 3.0 3.5 4.0 4.5 5.0

= V

DD

SUPPLY VOLTAGE (V)

DD

V

= 2V, GAIN = +1,

REF

BUFFERED

DD

, GAIN = +1, UNBUFFERED

TPC 13. Supply Current vs.
Supply Voltage

46

5

5V SOURCE

3V SOURCE

3

(V)

OUT

V

2

1

0

01 3446

SINK/SOURCE CURRENT (mA)

TPC 11. V

5V SINK

25

Source and

OUT

3V SINK

Sink Current Capability

1.0

T

= 25ⴗC

A

0.9

0.8

0.7

0.6

0.5

0.4

POWER-DOWN (␮A)

0.3

DD

I

0.2

0.1

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

2.0
VDD (V)

TPC 14. Power-Down Current vs.
Supply Voltage

1.0

0.9

0.8

0.7

0.6

0.5

(mA)

DD

I

0.4

0.3

0.2

0.1

0

ZERO SCALE FULL SCALE

HALF SCALE

DAC CODE

VDD = 5V

= 25ⴗC

T

A

TPC 12. Supply Current vs.
DAC Code

1.4

1.3

1.2

1.1

1.0

(mA)

DD

I

0.9

0.8

0.7

0.6

DECREASING

0 1.0

INCREASING

VDD = 3V

1.5 2.5 3.50.5 4.5 5.0

2.0 3.0 4.0
V

LOGIC

(V)

TA = 25ⴗC

= 5V

V

DD

TPC 15. Supply Current vs. Logic
Input Voltage for SCLK and DIN
Increasing and Decreasing

= 25ⴗC

T

A

5µs

= 5V

V

DD

= 5V

V

REF

V

A

OUT

CH1

SCLK

CH2

CH1 1V, CH2 5V, TIME BASE = 1␮s/DIV

TPC 16. Half-Scale Settling (1/4
to 3/4 Scale Code Change)

REV. B

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

V

CH1

CH2

CH1 2.00V, CH2 200mV, TIME BASE = 200␮s/DIV

DD

V

A

OUT

TPC 17. Power-On Reset to 0 V

–9–

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

V

A

CH1

CH2

CH1 500mV, CH2 5.00V, TIME BASE = 1␮s/DIV

OUT

PD

TPC 18. Exiting Power-Down
to Midscale

AD5308/AD5318/AD5328

35

30

25

20

15

FREQUENCY

10

5

0

0.6

TPC 19. I

= 3 V and V

V

DD

0.02

VDD = 5V
T

A

0.01

0

SS = 300

= 3V

V

DD

= 5V

V

DD

MEAN: 0.693798

MEAN: 1.02055

0.7 0.8 0.9 1.0 1.1
IDD (mA)

Histogram with

DD

= 25ⴗC

DD

= 5 V

2.50

2.49

(V)

OUT

V

2.48

2.47
1␮s/DIV

TPC 20. AD5328 Major-Code
Transition Glitch Energy

1mV/DIV

10

0

–10

–20

dB

–30

–40

–50

–60

10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

TPC 21. Multiplying Bandwidth
(Small-Signal Frequency Response)

–0.01

FULL-SCALE ERROR (V)

–0.02

01 3

25

V

46

(V)

REF

TPC 22. Full-Scale Error vs. V

REF

100ns/DIV

TPC 23. DAC-to-DAC Crosstalk

REV. B–10–

AD5308/AD5318/AD5328

TO OUTPUT
AMPLIFIER

R

R

R

R

R

FUNCTIONAL DESCRIPTION

The AD5308/AD5318/AD5328 are octal resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits, respectively. Each contains eight output buffer amplifiers
and is written to via a 3-wire serial interface. They operate
from single supplies of 2.5 V to 5.5 V, and the output buffer
amplifiers provide rail-to-rail output swing with a slew rate
of 0.7 V/µs. DACs A, B, C, and D share a common reference
input, V
reference input, V
buffered to draw virtually no current from the reference source,
may be unbuffered to give a reference input range from 0.25 V
to V
down mode in which all DACs may be turned off individually
with a high impedance output.

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor­string DAC followed by an output buffer amplifier. The voltage
at the V
sponding DAC. Figure 4 shows a block diagram of the DAC
architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by

where

D = decimal equivalent of the binary code that is loaded to the
DAC register:

0–255 for AD5308 (8 bits)
0–1023 for AD5318 (10 bits)
0–4095 for AD5328 (12 bits)

N = DAC resolution

INPUT

REGISTER

Resistor String

The resistor-string section is shown in Figure 5. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

ABCD. DACs E, F, G, and H share a common

REF

, or may come from VDD. The devices have a power-

DD

pin provides the reference voltage for the corre-

REF

V

DD

EFGH. Each reference input may be

REF

VD

×

=

V

RESISTOR

STRING

REF

REF

2

N

ABCD

REFERENCE
BUFFER

GAIN MODE

(GAIN = 1 OR 2)

OUTPUT

BUFFER AMPLIFIER

V

DD

BUF

DAC

REGISTER

V

OUT

Figure 4. Single DAC Channel Architecture

Figure 5. Resistor String

DAC Reference Inputs

There is a reference pin for each quad of DACs. The reference
inputs can be buffered from VDD, or unbuffered. The advantage
with the buffered input is the high impedance it presents to the
voltage source driving it. However, if the unbuffered mode is
used, the user can have a reference voltage as low as 0.25 V and
as high as V

since there is no restriction due to the headroom

DD

and footroom of the reference amplifier.

If there is a buffered reference in the circuit (e.g., REF192), there
is no need to use the on-chip buffers of the AD5308/AD5318/
AD5328. In unbuffered mode, the input impedance is still large
at typically 45 kΩ per reference input for 0 V to V
22 kΩ for 0 V to 2 V

REF

mode.

mode and

REF

Output Amplifier

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of V

, the gain of the output amplifier, the offset

REF

error, and the gain error.

If a gain of 1 is selected (GAIN bit = 0), the output range is

0.001 V to V

REF

.

If a gain of 2 is selected (GAIN bit = 1), the output range is

0.001 V to 2 V
mum output is limited to V

. Because of clamping, however, the maxi-

REF

– 0.001 V.

DD

The output amplifier is capable of driving a load of 2 kΩ to
GND or V

, in parallel with 500 pF to GND or VDD. The

DD

source and sink capabilities of the output amplifier can be seen
in the plot in TPC 11.

V

OUT

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB

A

(at eight bits) of 6 µs.

POWER-ON RESET

The AD5308/AD5318/AD5328 are provided with a power-on
reset function so that they power up in a defined state. The
power-on state is

• Normal operation

• Reference inputs unbuffered

• 0 V to V

output range

REF

• Output voltage set to 0 V

• LDAC bits set to LDAC high

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

REV. B

–11–

AD5308/AD5318/AD5328

SERIAL INTERFACE

The AD5308/AD5318/AD5328 are controlled over a versatile
3-wire serial interface that operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in Figure 1.

The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial
data transfer, SYNC should be taken low, observing the mini­mum SYNC to SCLK falling edge setup time, t

After SYNC

4.

goes low, serial data will be shifted into the device’s input shift
register on the falling edges of SCLK for 16 clock pulses.

To end the transfer, SYNC must be taken high after the falling
edge of the 16th SCLK pulse, observing the minimum SCLK
falling edge to SYNC rising edge time, t

.

7

After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer will be aborted and the DAC
input registers will not be updated.

Data is loaded MSB first (Bit 15). The first bit determines whether
it is a DAC write or a control function.

DAC Write

Here, the 16-bit word consists of one control bit and three
address bits followed by 8, 10, or 12 bits of DAC data, depending
on the device type. In the case of a DAC write, the MSB will be
a 0. The next three address bits determine whether the data is
for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC
G, or DAC H. The AD5328 uses all 12 bits of DAC data. The
AD5318 uses 10 bits and ignores the two LSBs. The AD5308
uses eight bits and ignores the last four bits. These ignored
LSBs should be set to 0. The data format is straight binary,
with all 0s corresponding to 0 V output and all 1s corresponding
to full-scale output.

Table I. Address Bits for the AD53x8

A2 (Bit 14) A1 (Bit 13) A0 (Bit 12) DAC Addressed

0 0 0 DAC A
0 0 1 DAC B
0 1 0 DAC C
0 1 1 DAC D
1 0 0 DAC E
1 0 1 DAC F
1 1 0 DAC G
1 1 1 DAC H

Control Functions

In the case of a control function, the MSB (Bit 15) will be a 1.
This is followed by two control bits, which determine the mode.
There are four different control modes, each of which is described
below. The write sequences for these modes are shown in Table II.

Reference and Gain Mode

This mode determines whether the reference for each group of
DACs is buffered, unbuffered, or from V

. It also determines

DD

the gain of the output amplifier. To set up the reference of both
groups, set the control bits to (00), set the GAIN bits, set the
BUF bits, and set the V

DD

bits.

BUF Controls whether the reference of a group of DACs is

buffered or unbuffered. The reference of the first group of
DACs (A, B, C, and D) is controlled by setting Bit 2, and
the second group of DACs (E, F, G, and H) is con­trolled by setting Bit 3.
0: Unbuffered reference.
1: Buffered reference.

GAIN The gain of the DACs is controlled by setting Bit 4 for

the first group of DACs (A, B, C, and D) and Bit 5 for
the second group of DACs (E, F, G, and H).
0: Output range of 0 V to V
1: Output range of 0 V to 2 V

REF

.

REF

.

BIT 15
(MSB)

A0

D/C

A1A2

D7 D6 D5 D4 D3 D2 D1 D0 0000

DATA BITS

Figure 6. AD5308 Input Shift Register Contents

BIT 15
(MSB)

A0

D/C

A1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A2

DATA BITS

Figure 7. AD5318 Input Shift Register Contents

BIT 15
(MSB)

A0

D/C

A1A2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10D11

DATA BITS

Figure 8. AD5328 Input Shift Register Contents

BIT 0
(LSB)

BIT 0
(LSB)

00

BIT 0
(LSB)

REV. B–12–

AD5308/AD5318/AD5328

Table II. Control Words for the AD53x8

D/C Control Bits
15 14 13 12 11 10 98765 4 3 2 1 0 Mode

(GAIN Bits)(BUF Bits)(V

10 0xxxxxxxE..H A..D E..H A..D E..H A..D and Reference Selection

10 1xxxxxxxx x x x 1/0 1/0 LDAC

(Channels)

11 0xxxxxHGF E D C B A Power-Down

(RESET)

11 11/0 x xxxxxx x x x x x Reset

Bits)Gain of Output Amplifier

DD

(LDAC Bits)

V

These bits are set when VDD is to be used as reference.

DD

The first group of DACs (A, B, C, and D) can be set
up to use V
DACs (E, F, G, and H) by setting Bit 1. The V

by setting Bit 0, and the second group of

DD

DD

bits

have priority over the BUF bits.

When V
unbuffered and with an output range of 0 V to V

is used as the reference, it will always be

DD

REF

,

regardless of the state of the GAIN and BUF bits.

LDAC Mode

LDAC mode controls LDAC, which determines when data is
transferred from the input registers to the DAC registers. There
are three options when updating the DAC registers, as shown in
Table III.

Table III. LDAC Mode

Bit Bit Bit Bits Bit Bit

15 14 13 12 .... 2 1 0 Description

10 1 x ..... x 0 0 LDAC Low

10 1 x ..... x 0 1 LDAC High

10 1 x ..... x 1 0 LDAC Single Update

10 1 x ..... x 1 1 Reserved

LDAC Low (00): This option sets LDAC permanently low,
allowing the DAC registers to be updated continuously.

LDAC High (01): This option sets LDAC permanently high.
The DAC registers are latched, and the input registers may
change without affecting the contents of the DAC registers.
This is the default option for this mode.

LDAC Single Update (10): This option causes a single pulse on
LDAC, updating the DAC registers once.

Reserved (11): Reserved.

Power-Down Mode

The individual channels of the AD5308/AD5318/AD5328 can
be powered down separately. The control mode for this is (10).
On completion of this write sequence, the channels that have
been set to 1 are powered down.

Reset Mode

This mode consists of two possible reset functions, as outlined
in Table IV.

Table IV. Reset Mode

Bit Bit Bit Bit Bit

15 14 13 12 11 .... 0 Description

1 110 x .... x DAC Data Reset

1 111 x .... x Data and Control Reset

DAC Data Reset: On completion of this write sequence, all
DAC registers and input registers are filled with 0s.

Data and Control Reset: This function carries out a DAC data
reset and also resets all the control bits (GAIN, BUF, V

DD

,

LDAC, and power-down channels) to their power-on conditions.

Low Power Serial Interface

To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.

LOAD DAC INPUT (LDAC) FUNCTION

Access to the DAC registers is controlled by both the LDAC
pin and the LDAC mode bits. The operation of the LDAC
function can be likened to the configuration shown in Figure 9.

EXTERNAL LDAC PIN

LDAC FUNCTION

INTERNAL LDAC MODE

Figure 9.

LDAC

Function

REV. B

–13–

AD5308/AD5318/AD5328

If the user wishes to update the DAC through software, the LDAC
pin should be tied high and the LDAC mode bits set as required.
Alternatively, if the user wishes to control the DAC through
hardware, i.e., the LDAC pin, the LDAC mode bits should be
set to LDAC high (default mode).

Use of the LDAC function enables double-buffering of the DAC
data, and the GAIN, BUF and V

bits. There are two ways in

DD

which the LDAC function can operate:
Synchronous LDAC: The DAC registers are updated after

new data is read in on the falling edge of the 16th SCLK pulse.
LDAC can be permanently low or pulsed as in Figure 1.

Asynchronous LDAC: The outputs are not updated at the
same time that the input registers are written to. When LDAC
goes low, the DAC registers are updated with the contents of
the input register.

DOUBLE-BUFFERED INTERFACE

The AD5308/AD5318/AD5328 DACs all have double-buffered
interfaces consisting of two banks of registers: input and DAC.
The input registers are connected directly to the input shift
register, and the digital code is transferred to the relevant input
register on completion of a valid write sequence. The DAC
registers contain the digital code used by the resistor strings.

When the LDAC pin is high and the LDAC bits are set to (01),
the DAC registers are latched and the input registers may change
state without affecting the contents of the DAC registers. How­ever, when the LDAC bits are set to (00) or when the LDAC
pin is brought low, the DAC registers become transparent and
the contents of the input registers are transferred to them.

The double-buffered interface is useful if the user requires simulta­neous updating of all DAC outputs. The user may write to seven
of the input registers individually and then, by bringing LDAC
low when writing to the remaining DAC input register, all out­puts will update simultaneously.

These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time LDAC was low. Normally, when LDAC is brought
low, the DAC registers are filled with the contents of the input
registers. In the case of the AD5308/AD5318/AD5328, the part
will update the DAC register only if the input register has been
changed since the last time the DAC register was updated, thereby
removing unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5308/AD5318/AD5328 have low power consumption,
typically dissipating 2.4 mW with a 3 V supply and 5 mW with a
5 V supply. Power consumption can be further reduced when the
DACs are not in use by putting them into power-down mode,
which was described previously.

When in default mode, all DACs work normally with a typical
power consumption of 1 mA at 5 V (800 µA at 3 V). However,
when all DACs are powered down, i.e., in power-down mode,
the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not
only does the supply current drop, but the output stage is also
internally switched from the output of the amplifier, making it
open-circuit. This has the advantage that the output is three­state while the part is in power-down mode, and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. The output stage is illustrated in Figure 10.

The bias generator, the output amplifiers, the resistor string,
and all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. In fact, it is pos­sible to load new data to the input registers and DAC registers
during power-down. The DAC outputs will update as soon as
the device comes out of power-down mode. The time to exit
power-down is typically 2.5 µs for V

= 3 V.

V

DD

RESISTOR-

STRING DAC

= 5 V and 5 µs when

DD

AMPLIFIER

POWER-DOWN

CIRCUITRY

V

OUT

Figure 10. Output Stage during Power-Down

MICROPROCESSOR INTERFACING
ADSP-2101/ADSP-2103 to AD5308/AD5318/AD5328 Interface

Figure 11 shows a serial interface between the AD5308/AD5318/
AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 SPORT
is programmed through the SPORT control register and should
be configured as follows: internal clock operation, active-low
framing, and 16-bit word length. Transmission is initiated by
writing a word to the Tx register after the SPORT has been
enabled. The data is clocked out on each rising edge of the
DSP’s serial clock and clocked into the AD5308/AD5318/
AD5328 on the falling edge of the DAC’s SCLK.

ADSP-2101/

ADSP-2103*

TFS

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5308/
AD5318/

AD5328*

SYNC

DIN

SCLK

Figure 11. ADSP-2101/ADSP-2103 to AD5308
AD5318/AD5328 Interface

68HC11/68L11 to AD5308/AD5318/AD5328 Interface

Figure 12 shows a serial interface between the AD5308/AD5318/
AD5328 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5308/AD5318/
AD5328, while the MOSI output drives the serial data line
(DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for the correct operation of
this interface are as follows: the 68HC11/68L11 should be
configured so that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is being transmitted to the DAC, the SYNC line is
taken low (PC7). When the 68HC11/68L11 is configured as
above, data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11/68L11 is transmit­ted in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To load data
to the AD5308/AD5318/AD5328, PC7 is left low after the first
eight bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.

REV. B–14–

AD5308/AD5318/AD5328

68HC11/68L11*

AD5308/
AD5318/

AD5328*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SCLK

DIN

Figure 12. 68HC11/68L11 to AD5308/AD5318/
AD5328 Interface

80C51/80L51 to AD5308/AD5318/AD5328 Interface

Figure 13 shows a serial interface between the AD5308/AD5318/
AD5328 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives
SCLK of the AD5308/AD5318/AD5328, while RxD drives the
serial data line of the part. The SYNC signal is again derived
from a bit programmable pin on the port. In this case, port line
P3.3 is used. When data is transmitted to the AD5308/AD5318/
AD5328, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus, only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low
after the first eight bits are transmitted, and a second write cycle
is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
outputs the serial data in a format that has the LSB first. The
AD5308/AD5318/AD5328 requires its data with the MSB as
the first bit received. The 80C51/80L51 transmit routine should
take this into account.

80C51/80L51*

P3.3

TxD

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5308/
AD5318/

AD5328*

SYNC

SCLK

DIN

Figure 13. 80C51/80L51 to AD5308/AD5318/
AD5328 Interface

MICROWIRE to AD5308/AD5318/AD5328 Interface

Figure 14 shows an interface between the AD5308/AD5318/
AD5328 and any MICROWIRE compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5308/AD5318/AD5328 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

CS

SK

SO

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5308/
AD5318/
AD5328*

SYNC

SCLK

DIN

APPLICATIONS
Typical Application Circuit

The AD5308/AD5318/AD5328 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0.25 V to V

DD

.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780, ADR381, and REF192 (2.5 V references). For 2.5 V
operation, a suitable external reference would be the AD589
and AD1580 (1.2 V band gap references). Figure 15 shows a
typical setup for the AD5308/AD5318/AD5328 when using an
external reference.

= 2.5V TO 5.5V

V

DD

1␮F

SERIAL

INTERFACE

10␮F

V

REF

V

REF

AD5308/AD5318/

SCLK

DIN

SYNC

ABCD

EFGH

AD5328

GND

A

V

OUT

V

B

OUT

V

G

OUT

V

H

OUT

V

IN

V

OUT

EXT
REF

AD780/ADR3811/REF192
WITH V

DD

AD589/AD1580 WITH

= 2.5V

V

DD

0.1␮F

= 5V OR

Figure 15. AD5308/AD5318/AD5328 Using a 2.5 V
External Reference

Driving VDD from the Reference Voltage

If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference input to V

. As this supply may be noisy

DD

and not very accurate, the AD5308/AD5318/AD5328 may be
powered from a voltage reference. For example, using a 5 V
reference, such as the REF195, will work because the REF195
will output a steady supply voltage for the AD5308/AD5318/
AD5328. The typical current required from the REF195 is a
1 µA supply current and ≈ 112 µA into the reference inputs (if
unbuffered); this is with no load on the DAC outputs. When the
DAC outputs are loaded, the REF195 also needs to supply the
current to the loads. The total current required (with a 10 kΩ
load on each output) is

122 85 10 522./.mA V k mA+

()

=Ω

The load regulation of the REF195 is typically 2.0 ppm/mA,
which results in an error of 10.4 ppm (52 µV) for the 5.22 mA
current drawn from it. This corresponds to a 0.003 LSB error at
eight bits and 0.043 LSB error at 12 bits.

Bipolar Operation Using the AD5308/AD5318/AD5328

The AD5308/AD5318/AD5328 have been designed for single­supply operation, but a bipolar output range is also possible
using the circuit in Figure 16. This circuit will give an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820, the AD8519, or an OP196
as the output amplifier.

Figure 14. MICROWIRE to AD5308/AD5318/
AD5328 Interface

REV. B

–15–

AD5308/AD5318/AD5328

74HC139

V

CC

V

DD

ENABLE

CODED
ADDRESS

1G

1A

1B

DGND

1Y0
1Y1
1Y2
1Y3

SCLK

DIN

SYNC

DIN
SCLK

V

OUT

A

V

OUT

B

V

OUT

G

V

OUT

H

SYNC

DIN
SCLK

SYNC

DIN
SCLK

SYNC

DIN
SCLK

AD5308

V

OUT

A

V

OUT

B

V

OUT

G

V

OUT

H

V

OUT

A

V

OUT

B

V

OUT

G

V

OUT

H

V

OUT

A

V

OUT

B

V

OUT

G

V

OUT

H

AD5308

AD5308

AD5308

R2

10k⍀

ⴙ5V

A

–5V

B

C

H

AD820/
AD8519/
OP196

ⴞ5V

+6V TO +16V

V

IN

REF192

V

OUT

GND

10␮F

1␮F

0.1␮F

ⴙ5V

R1

10k⍀

V

DD

V

SCLK

SERIAL

OUT

V

OUT

V

OUT

V

OUT

SYNC

AD5308/AD5318/

AD5328

V

ABCD

REF

V

EFGH

REF

GND

DIN

INTERFACE

Figure 16. Bipolar Operation with the AD5308/
AD5318/AD5328

The output voltage for any input code can be calculated as
follows:



REFIN D R R

()

OUT



=



R REFIN R R

121–/



V

N

×

×+

212

()

×

()







where

D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.

with

REFIN = 5 V, R1 = R2 = 10 kΩ:

VDV

=×

10 2 5/–

()

OUT

N

Opto-Isolated Interface for Process Control Applications

The AD5308/AD5318/AD5328 have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5308/AD5318/AD5328 from the controller. This can easily
be achieved by using opto-isolators that will provide isolation in
excess of 3 kV. The actual data rate achieved may be limited by
the type of optocouplers chosen. The serial loading structure of
the AD5308/AD5318/AD5328 makes them ideally suited for use
in opto-isolated applications. Figure 17 shows an opto-isolated
interface to the AD5308/AD5318/AD5328 where DIN, SCLK,
and SYNC are driven from optocouplers. The power supply to
the part also needs to be isolated. This is done by using a trans­former. On the DAC side of the transformer, a 5 V regulator
provides the 5 V supply required for the AD5308/AD5318/
AD5328.

5V

POWER

SCLK

SYNC

DIN

REGULATOR

V

DD

10k⍀

V

DD

10k⍀

V

DD

10k⍀

SCLK

AD5308/AD5318/

AD5328

SYNC

DIN

V

DD

GND

10␮F

0.1␮F

V

ABCD

REF

V

EFGH

REF

A

V

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

E

OUT

V

F

OUT

V

G

OUT

V

H

OUT

Figure 17. AD5308/AD5318/AD5328 in an
Opto-Isolated Interface

Decoding Multiple AD5308/AD5318/AD5328s

The SYNC pin on the AD5308/AD5318/AD5328 can be used
in applications to decode a number of DACs. In this applica­tion, the DACs in the system receive the same serial clock and
serial data but only the SYNC to one of the devices will be
active at any one time, allowing access to four channels in
this 16-channel system. The 74HC139 is used as a 2-to-4 line
decoder to address any of the DACs in the system. To prevent
timing errors from occurring, the enable input should be brought
to its inactive state while the coded-address inputs are changing
state. Figure 18 shows a diagram of a typical setup for decoding
multiple AD5308 devices in a system.

Figure 18. Decoding Multiple AD5308 Devices in a System

REV. B–16–

AD5308/AD5318/AD5328

Table V. Overview of AD53xx Serial Devices

Part No. Resolution DNL V

Pins Settling Time (␮s) Interface Package Pins

REF

SINGLES

AD5300 8 ±0.25 0 (V
AD5310 10 ±0.50 0 (V
AD5320 12 ±1.00 0 (V

AD5301 8 ±0.25 0 (V
AD5311 10 ±0.50 0 (V
AD5321 12 ±1.00 0 (V

= VDD) 4 SPI SOT-23, MSOP 6, 8

REF

= VDD) 6 SPI SOT-23, MSOP 6, 8

REF

= VDD) 8 SPI SOT-23, MSOP 6, 8

REF

= VDD) 6 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 7 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 8 2-Wire SOT-23, MSOP 6, 8

REF

DUALS

AD5302 8 ±0.25 2 6 SPI MSOP 10
AD5312 10 ±0.50 2 7 SPI MSOP 10
AD5322 12 ±1.00 2 8 SPI MSOP 10

AD5303 8 ±0.25 2 6 SPI TSSOP 16
AD5313 10 ±0.50 2 7 SPI TSSOP 16
AD5323 12 ±1.00 2 8 SPI TSSOP 16

QUADS

AD5304 8 ±0.25 1 6 SPI MSOP 10
AD5314 10 ±0.50 1 7 SPI MSOP 10
AD5324 12 ±1.00 1 8 SPI MSOP 10

AD5305 8 ±0.25 1 6 2-Wire MSOP 10
AD5315 10 ±0.50 1 7 2-Wire MSOP 10
AD5325 12 ±1.00 1 8 2-Wire MSOP 10

AD5306 8 ±0.25 4 6 2-Wire TSSOP 16
AD5316 10 ±0.50 4 7 2-Wire TSSOP 16
AD5326 12 ±1.00 4 8 2-Wire TSSOP 16

AD5307 8 ±0.25 2 6 SPI TSSOP 16
AD5317 10 ±0.50 2 7 SPI TSSOP 16
AD5327 12 ±1.00 2 8 SPI TSSOP 16

OCTALS

AD5308 8 ±0.25 2 6 SPI TSSOP 16
AD5318 10 ±0.50 2 7 SPI TSSOP 16
AD5328 12 ±1.00 2 8 SPI TSSOP 16

Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.

Table VI. Overview of AD53xx Parallel Devices

Part No. Resolution DNL V

Pins Settling Time (␮s) Additional Pin Functions Package Pins

REF

SINGLES BUF GAIN HBEN CLR

AD5330 8 ± 0.25 1 6 ✓✓ ✓ TSSOP 20
AD5331 10 ± 0.50 1 7 ✓✓TSSOP 20
AD5340 12 ± 1.00 1 8 ✓✓ ✓ TSSOP 24
AD5341 12 ± 1.00 1 8 ✓✓ ✓ ✓ TSSOP 20

DUALS

AD5332 8 ± 0.25 2 6 ✓ TSSOP 20
AD5333 10 ± 0.50 2 7 ✓✓ ✓ TSSOP 24
AD5342 12 ± 1.00 2 8 ✓✓ ✓ TSSOP 28
AD5343 12 ± 1.00 1 8 ✓✓TSSOP 20

QUADS

AD5334 8 ± 0.25 2 6 ✓✓TSSOP 24
AD5335 10 ± 0.50 2 7 ✓✓TSSOP 24
AD5336 10 ± 0.50 4 7 ✓✓TSSOP 28
AD5344 12 ± 1.00 4 8 TSSOP 28

REV. B

–17–

AD5308/AD5318/AD5328

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40
BSC

SEATING

PLANE

0.20

0.09

0.75

8ⴗ
0ⴗ

0.60

0.45

REV. B–18–

AD5308/AD5318/AD5328

Revision History

Location Page

11/03—Data Sheet changed from REV. A to REV. B.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Changes to Y axis on TPCs 12, 13, and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

8/03—Data Sheet changed from REV. 0 to REV. A.

Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

REV. B

–19–

C02812–0–11/03(B)

–20–