Page 1
54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
D
Members of the Texas Instruments
Widebus
D
Inputs Are TTL-Voltage Compatible
D
Noninverting Outputs
D
Two 16-Bit, Back-to-Back Registers Store
Family
Data Flowing in Both Directions
D
Flow-Through Architecture Optimizes
PCB Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
description
The ’ACT16952 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. They can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in registers on the low-to-high
transition of the clock (CLKAB or CLKBA) input,
provided that the clock-enable (CEAB
input is low. Taking the output-enable (OEAB or
OEBA
) input low accesses the data on either port.
or CEBA)
54ACT16952 . . . WD PACKAGE
74ACT16952 . . . DL PACKAGE
1OEAB
1CLKAB
1CEAB
2CEAB
2CLKAB
2OEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2CLKBA
2OEBA
To avoid false clocking of the flip-flops, CEAB (or
CEBA) should not be switched from low to high
while CLKAB (or CLKBA) is low.
The 74ACT16952 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16952 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16952 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
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54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
CEAB
†
A-to-B data flow is shown; B-to-A data flow is
similar but uses CEBA
‡
Level of B before the indicated steady-state
input conditions were established
CLKAB OEAB A
H X L X B
X HLXB
L ↑ LL L
L ↑ LH H
X X H X Z
, CLKBA, and OEBA.
†
OUTPUT
B
‡
0
‡
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
logic symbol
†
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
56
54
55
1
3
2
29
31
30
28
26
27
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
EN3
G1
EN4
G2
EN9
G7
EN10
G8
3
6D
9
12D
10
5D
4
11D
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1OEBA
1CEBA
1CLKBA 1C5
1OEAB
1CEAB
1CLKAB 2C6
2OEBA
2CEBA
2CLKBA 7C11
2OEAB
2CEAB
2CLKAB 8C12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
logic diagram (positive logic)
1OEBA
1CEBA
1CLKBA
1OEAB
1CEAB
1CLKAB
1A1
56
54
55
1
3
2
5
C1
1D
To Seven Other Channels
C1
1D
52
1B1
2OEBA
2CEBA
2CLKBA
2OEAB
2CEAB
2CLKAB
2A1
29
31
30
28
26
27
15
C1
1D
To Seven Other Channels
C1
1D
42
2B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
UNIT
54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through VCC or GND ±400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package 1.4 W. . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
54ACT16952 74ACT16952
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
CC
CC
0 V
0 V
CC
CC
V
V
†
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
54ACT16952, 74ACT16952
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
VOHI
mA
V
I
A
VOLI
mA
V
UNIT
t
S
CLK↑
ns
t
Hold ti
CLK↑
ns
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50 µ
OH
= –24
OH
IOH = –50 mA
IOH = –75 mA
= 50 µ
OL
= 24
OL
IOL = 50 mA
IOL = 75 mA
I
I
I
OZ
I
CC
∆I
C
C
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Control inputs VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
‡
A or B ports VO = VCC or GND 5.5 V ±0.5 ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 8 80 80 µA
§
CC
Control inputs VI = VCC or GND 5 V 3 pF
i
A or B ports VO = VCC or GND 5 V 12 pF
io
One input at 3.4 V ,
Other inputs at VCC or GND
†
†
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.8 3.8
5.5 V 4.94 4.8 4.8
5.5 V
5.5 V 3.85 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.44 0.44
5.5 V 0.36 0.44 0.44
5.5 V
5.5 V 1.65 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT16952 74ACT16952
MIN TYP MAX MIN MAX MIN MAX
timing requirements over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted)
CC
TA = 25°C 54ACT16952 74ACT16952
MIN MAX MIN MAX MIN MAX
f
clock
t
w
su
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Clock frequency 0 75 0 75 0 75 MHz
Pulse duration, CLK high or low 6.7 6.7 6.7 ns
etup time before
me after
Data 5 5 5
CEAB or CEBA 6.5 6.5 6.5
Data 1 1 1
CEAB or CEBA 0 0 0
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
PARAMETER
UNIT
CLK
A or B
ns
CEBA
CEAB
A or B
ns
OEBA
OEAB
A or B
ns
OEBA
OEAB
A or B
ns
54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
or
or
or
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per transceiver Outputs enabled CL = 50 pF, f = 1 MHz 55 pF
pd
TA = 25°C 54ACT16952 74ACT16952
MIN TYP MAX MIN MAX MIN MAX
75 75 75 MHz
4.7 8.5 10.7 4.7 11.8 4.7 11.8
4.9 8.7 10.5 4.9 11.7 4.9 11.7
4.7 8.5 10.7 4.7 11.8 4.7 11.8
4.9 8.7 10.5 4.9 11.7 4.9 11.7
3.4 8.1 10.2 3.4 11.2 3.4 11.2
4.2 9.6 11.8 4.2 13 4.2 13
5.2 7.5 8.9 5.2 9.4 5.2 9.4
4.5 6.7 8.2 4.5 8.7 4.5 8.7
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
54ACT16952, 74ACT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCAS159C – JANUARY 1991 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
2 × V
Open
GND
CC
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
t
w
Input
In-Phase
Output
Out-of-Phase
NOTES: A. CL includes probe and jig capacitance.
1.5 V 1.5 V
VOLTAGE WAVEFORMS
Input
t
PLH
t
PHL
Output
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
50% V
CC
50% V
CC
VOLTAGE WAVEFORMS
t
PHL
50% V
t
PLH
50% V
3 V
0 V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
(see Note B)
Data Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
CC
t
t
t
su
1.5 V
VOLTAGE WAVEFORMS
1.5 V
PZL
PZH
VOLTAGE WAVEFORMS
1.5 V
t
PLZ
50% V
t
PHZ
50% V
CC
CC
t
h
1.5 V
1.5 V
20% V
80% V
CC
CC
3 V
0 V
3 V
0 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
8
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Page 9
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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