Datadelay PDU108H-3C3, PDU108H-3MC3, PDU108H-40, PDU108H-40C3, PDU108H-40M Datasheet

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Datadelay PDU108H-3C3, PDU108H-3MC3, PDU108H-40, PDU108H-40C3, PDU108H-40M Datasheet
IN OUT A2 A1 A0 ENB VEE GND

PDU108H

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU108H)

data 3 ® delay

devices, inc.

FEATURES

Digitally programmable in 8 delay steps

Monotonic delay-versus-address variation

Precise and stable delays

Input & outputs fully 10KH-ECL interfaced & buffered

Fits standard 16-pin DIP socket

PACKAGES

GND

 

1

16

 

GND

 

 

 

 

 

 

GND

1

16

GND

 

 

ENB

 

 

2

15

 

OUT

ENB

2

15

OUT

 

 

 

 

 

 

 

 

 

 

N/C

3

14

N/C

 

 

 

 

 

 

 

N/C

4

13

N/C

 

 

 

 

 

 

 

N/C

5

12

N/C

 

 

 

 

 

 

 

IN

6

11

N/C

IN

 

6

 

 

 

A0

7

10

A1

 

 

 

 

VEE

8

9

A2

 

 

 

 

A0

 

 

7

10

 

A1

 

 

 

 

 

 

 

 

 

 

 

VEE

 

 

8

9

 

A2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDU108H-xx DIP

PDU108H-xxC3

SMD

PDU108H-xxM Military DIP

PDU108H-xxMC3

Mil SMD

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU108H-series device is a 3-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A2-A0) according to the following formula:

TDA = TD0 + TINC * A

where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. The enable pin (ENB) is held LOW during

normal operation. When this signal is brought HIGH, OUT is forced into a LOW state. latched and must remain asserted during normal operation.

Signal Input

Signal Output

Address Bit 2

Address Bit 1

Address Bit 0

Output Enable

-5 Volts

Ground

The address is not

SERIES SPECIFICATIONS

Total programmed delay tolerance: 5% or 1ns,

whichever is greater

Inherent delay (TD0): 2.8ns typical

Setup time and propagation delay:

Address to input setup (TAIS): 3.6ns Disable to output delay (TDISO): 1.7ns typical

Operating temperature: 0° to 70° C

Temperature coefficient: 100PPM/°C (excludes TD0)

Supply voltage VEE: -5VDC ± 5%

Power Dissipation: 290mw typical (no load)

Minimum pulse width: 25% of total delay

DASH NUMBER SPECIFICATIONS

Part

Incremental Delay

Total

Number

Per Step (ns)

Delay (ns)

PDU108H-.5

0.5

± 0.3

3.5 ± 1.0

 

PDU108H-1

1.0

± 0.4

7.0 ± 1.0

 

PDU108H-2

2.0

± 0.4

14

± 1.0

 

PDU108H-3

3.0

± 0.5

21

± 1.0

 

PDU108H-5

5.0

± 0.6

35

± 1.7

 

PDU108H-10

10.0

± 1.0

70

± 3.5

 

PDU108H-20

20.0

± 1.5

140 ± 7.0

 

PDU108H-40

40.0

± 2.0

280

± 14.0

 

PDU108H-50

50.0

± 2.5

350

± 17.5

 

NOTE: Any dash number between .5 and 50 not shown is also available.

©2001 Data Delay Devices

Doc #97043

DATA DELAY DEVICES, INC.

1

10/1/01

3 Mt. Prospect Ave. Clifton, NJ 07013

PDU108H

APPLICATION NOTES

ADDRESS UPDATE

The PDU108H is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.

After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed.

A similar situation occurs when using the ENB signal to disable the output while IN is active. In this case, the unit must be held in the disabled state until the device is able to “clear” itself. This is achieved by holding the ENB signal high and the IN signal low for a time given by:

TDISH = Ai * TINC

Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of

spurious signals persists until the required TDISH has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.

When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.

Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

A2-A0

A i-1

 

Ai

TAENS

 

TOAX

TAIS

ENB

 

 

 

TENIS

PWIN

 

TDISH

IN

 

 

 

TDA

PWOUT

 

TDISO

OUT

Figure 1: Timing Diagram

Doc #97043

DATA DELAY DEVICES, INC.

2

10/1/01

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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