DS1245Y/AB
1024k Nonvolatile SRAM
www.dalsemi.com
FEATURES
10 years minimum data retention in the absence of external power
Data is automatically protected during power loss
Replaces 128k x 8 volatile static RAM, EEPROM or Flash memory
Unlimited write cycles
Low-power CMOS
Read and write access times as fast as 70 ns
Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time
Full ± 10% VCC operating range (DS1245Y)
Optional ± 5% VCC operating range (DS1245AB)
Optional industrial temperature range of -40° C to +85° C, designated IND
JEDEC standard 32-pin DIP package
New PowerCap Module (PCM) package
-Directly surface-mountable module
-Replaceable snap-on PowerCap provides lithium backup battery
-Standardized pinout for all nonvolatile SRAM products
-Detachment feature on PowerCap allows easy removal using a regular screwdriver
PIN ASSIGNMENT
NC |
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1 |
32 |
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VCC |
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A16 |
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31 |
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A15 |
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A14 |
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30 |
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NC |
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A12 |
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29 |
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WE |
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A7 |
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28 |
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A13 |
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A6 |
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A8 |
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A5 |
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A9 |
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A4 |
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A11 |
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A3 |
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OE |
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A2 |
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23 |
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A10 |
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A1 |
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22 |
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CE |
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A0 |
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21 |
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DQ7 |
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DQ0 |
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13 |
20 |
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DQ6 |
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DQ1 |
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19 |
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DQ5 |
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DQ2 |
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15 |
18 |
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DQ4 |
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GND |
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16 |
17 |
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DQ3 |
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32-PIN ENCAPSULATED PACKAGE
740 MIL EXTENDED
NC |
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1 |
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34 |
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NC |
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A15 |
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2 |
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33 |
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NC |
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A16 |
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3 |
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32 |
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A14 |
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NC |
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4 |
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31 |
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A13 |
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VCC |
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5 |
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30 |
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A12 |
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WE |
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6 |
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29 |
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A11 |
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OE |
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7 |
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28 |
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A10 |
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CE |
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8 |
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27 |
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A9 |
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DQ7 |
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9 |
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26 |
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A8 |
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DQ6 |
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10 |
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25 |
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A7 |
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DQ5 |
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11 |
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24 |
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A6 |
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DQ4 |
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12 |
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23 |
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A5 |
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DQ3 |
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GND VBAT |
22 |
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A4 |
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DQ2 |
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14 |
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21 |
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A3 |
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DQ1 |
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20 |
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A2 |
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DQ0 |
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16 |
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19 |
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A1 |
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GND |
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17 |
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18 |
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A0 |
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34-PIN POWERCAP MODULE (PCM) (USES DS9034PC POWERCAP)
PIN DESCRIPTION
A0 - A16 |
- Address Inputs |
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DQ0 - DQ7 |
- Data In/Data Out |
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- Chip Enable |
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CE |
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- Write Enable |
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WE |
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- Output Enable |
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OE |
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VCC |
- Power (+5V) |
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GND |
- Ground |
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NC |
- No Connect |
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111899 |
DS1245Y/AB
DESCRIPTION
The DS1245 1024k Nonvolatile SRAMs are1,048,576-bit, fully static, nonvolatile SRAMs organized as 131,072 words by 8 bits. Each complete NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. DIP-package DS1245 devices can be used in place of existing 128k x 8 static RAMs directly conforming to the popular bytewide 32-pin DIP standard. DS1245 devices in the PowerCap Module package are directly surface mountable and are normally paired with a DS9034PC PowerCap to form a complete Nonvolatile SRAM module. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
READ MODE
The DS1245 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 - A16) defines which of the 131,072 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC (Access Time) after the last address input signal is stable, providing that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either tCO for CE or tOE for OE rather than address access.
WRITE MODE
The DS1245 executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The DS1245AB provides full functional capability for VCC greater than 4.75 volts and write protects by 4.5 volts. The DS1245Y provides full functional capability for VCC greater than 4.5 volts and writeprotects by 4.25 volts. Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static RAMs constantly monitor VCC. Should the supply voltage decay, the NV SRAMs automatically write-protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.75 volts for the DS1245AB and 4.5 volts for the DS1245Y.
FRESHNESS SEAL
Each DS1245 device is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than 4.25 volts, the lithium energy source is enabled for battery back-up operation.
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DS1245Y/AB
PACKAGES
The DS1245 devices are available in two packages: 32-pin DIP and 34-pin PowerCap Module (PCM). The 32-pin DIP integrates a lithium battery, an SRAM memory and a nonvolatile control function into a single package with a JEDEC-standard 600-mil DIP pinout. The 34-pin PowerCap Module integrates SRAM memory and nonvolatile control along with contacts for connection to the lithium battery in the DS9034PC PowerCap. The PowerCap Module package design allows a DS1245 PCM device to be surface mounted without subjecting its lithium backup battery to destructive high-temperature reflow soldering. After a DS1245 PCM is reflow soldered, a DS9034PC PowerCap is snapped on top of the PCM to form a complete Nonvolatile SRAM module. The DS9034PC is keyed to prevent improper attachment. DS1245 PowerCap Modules and DS9034PC PowerCaps are ordered separately and shipped in separate containers. See the DS9034PC data sheet for further information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C, -40°C to +85°C for Ind parts -40°C to +70°C, -40°C to +85°C for Ind parts 260°C for 10 seconds
*This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS |
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(tA: See Note 10) |
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PARAMETER |
SYMBOL |
MIN |
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TYP |
MAX |
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UNITS |
NOTES |
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DS1245AB Power Supply Voltage |
VCC |
4.75 |
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5.0 |
5.25 |
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V |
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DS1245Y Power Supply Voltage |
VCC |
4.5 |
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5.0 |
5.5 |
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V |
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Logic 1 |
VIH |
2.2 |
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VCC |
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V |
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Logic 0 |
VIL |
0.0 |
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0.8 |
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V |
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DC ELECTRICAL |
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(VCC=5V ± |
5% for DS1245AB) |
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CHARACTERISTICS |
(tA: See Note 10) (VCC=5V ± |
10% for DS1245Y) |
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PARAMETER |
SYMBOL |
MIN |
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TYP |
MAX |
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UNITS |
NOTES |
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Input Leakage Current |
IIL |
-1.0 |
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+1.0 |
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I/O Leakage Current |
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≥ VIH ≤ VCC |
IIO |
-1.0 |
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+1.0 |
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CE |
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Output Current @ 2.4V |
IOH |
-1.0 |
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mA |
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Output Current @ 0.4V |
IOL |
2.0 |
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mA |
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Standby Current |
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=2.2V |
ICCS1 |
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5.0 |
10.0 |
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mA |
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CE |
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Standby Current |
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=VCC-0.5V |
ICCS2 |
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3.0 |
5.0 |
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mA |
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Operating Current |
ICCO1 |
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85 |
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mA |
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Write Protection Voltage (DS1245AB) |
VTP |
4.50 |
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4.62 |
4.75 |
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V |
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Write Protection Voltage (DS1245Y) |
VTP |
4.25 |
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4.37 |
4.5 |
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V |
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DS1245Y/AB |
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CAPACITANCE |
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(tA=25° C) |
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PARAMETER |
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Input Capacitance |
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CIN |
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5 |
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10 |
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pF |
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Input/Output Capacitance |
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CI/O |
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10 |
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pF |
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AC ELECTRICAL |
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(VCC=5V ± |
5% for DS1245AB) |
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CHARACTERISTICS |
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(tA: See Note 10) (VCC=5V ± |
10% for DS1245Y) |
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DS1245AB-70 |
DS1245AB-85 |
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DS1245Y-70 |
DS1245Y-85 |
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PARAMETER |
SYMBOL |
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MIN |
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MAX |
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MIN |
MAX |
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Read Cycle Time |
tRC |
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70 |
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85 |
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Access Time |
tACC |
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70 |
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85 |
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to Output Valid |
tOE |
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35 |
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45 |
ns |
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OE |
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to Output Valid |
tCO |
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70 |
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85 |
ns |
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CE |
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to Output Active |
tCOE |
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5 |
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ns |
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5 |
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OE |
CE |
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Output High Z from Deselection |
tOD |
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25 |
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30 |
ns |
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Output Hold from Address Change |
tOH |
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5 |
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5 |
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Write Cycle Time |
tWC |
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70 |
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85 |
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Write Pulse Width |
tWP |
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55 |
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65 |
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3 |
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Address Setup Time |
tAW |
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0 |
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0 |
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ns |
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Write Recovery Time |
tWR1 |
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5 |
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5 |
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ns |
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12 |
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tWR2 |
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15 |
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15 |
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ns |
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13 |
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Output High Z from |
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tODW |
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25 |
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30 |
ns |
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5 |
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WE |
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Output Active from |
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tOEW |
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5 |
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5 |
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ns |
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5 |
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WE |
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Data Setup Time |
tDS |
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30 |
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35 |
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ns |
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4 |
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Data Hold Time |
tDH1 |
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0 |
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0 |
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ns |
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12 |
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tDH2 |
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10 |
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10 |
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ns |
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13 |
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