Dallas Semiconductor DS1005S-75-T-R, DS1005S-75, DS1005S-60-T-R, DS1005S-60, DS1005S-250-T-R Datasheet

DS1005

5-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

5 taps equally spaced

Delay tolerance ±2 ns or ±3%, whichever is greater

Stable and precise over temperature and voltage range

Leading and trailing edge accuracy

Economical

Auto-insertable, low profile

Standard 14-pin DIP, 8-pin DIP, or 16-pin SOIC

Tape and reel available for surface-mount

Low-power CMOS

TTL/CMOS compatible

Vapor phase, IR and wave solderability

Custom delays available

Quick turn prototypes

Extended temperature range available

PIN ASSIGNMENT

IN		1			14			VCC			IN						1		16			VCC
NC			2		13			NC			NC						2		15			NC
NC			3		12			TAP 1			NC						3		14			NC
TAP 2			4		11			NC		TAP 2							4		13			TAP 1
NC					10			TAP 3			NC						5		12			NC
		5
TAP 4					9			NC		TAP 4							6		11			TAP 3
		6
GND			7		8			TAP 5			NC						7		10			NC
DS1005			14-Pin DIP			(300-mil)					GND						8		9			TAP 5
See Mech. Drawings Section
											DS1005S 16-Pin SOIC
																	(300-mil)
											See Mech. Drawings Section
					IN				1	8							VCC
					TAP 2				2	7							TAP 1
					TAP 4				3	6							TAP 3
					GND				4	5							TAP 5

DS1005M 8-Pin DIP (300-mil)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-TAP 5 - TAP Output Number

VCC	- +5 Volts
GND	- Ground
NC	- No Connection
IN	- Input

DESCRIPTION

The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns to 250 ns, with an accuracy of ± 2 ns or ± 3%, whichever is greater. This device is offered in a standard 14pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call (972) 371–4348.

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111799

DS1005

LOGIC DIAGRAM Figure 1

PART NUMBER DELAY TABLE (tPHL, tPLH) Table 1

PART NO.	TAP 1	TAP 2	TAP 3	TAP 4	TAP 5
DS1005-60	12 ns	24 ns	36 ns	48 ns	60 ns
DS1005-75	15 ns	30 ns	45 ns	60 ns	75 ns
DS1005-100	20 ns	40 ns	60 ns	80 ns	100 ns
DS1005-125	25 ns	50 ns	75 ns	100 ns	125 ns
DS1005-150	30 ns	60 ns	90 ns	120 ns	150 ns
DS1005-175	35 ns	70 ns	105 ns	140 ns	175 ns
DS1005-200	40 ns	80 ns	120 ns	160 ns	200 ns
DS1005-250	50 ns	100 ns	150 ns	200 ns	250 ns

Custom delays available

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