dallas semiconductor DS1000-IND service manual

DS1000-IND

DS1000-IND

Industrial Temperature Range 5-Tap Silicon Delay Line

www.dalsemi.com

FEATURES

All-silicon time delay

5 taps equally spaced

Delays are stable and precise

Both leading and trailing edge accuracy

Delay tolerance ± 5% or ± 2 ns, whichever is greater (@25° C)

Delays characterized over -40°C to +85°C temperature range (± 2 ns or ± 8%)

Low-power CMOS

TTL/CMOS-compatible

Vapor phase, IR and wave solderable

Custom delays available

Fast turn prototypes

PIN ASSIGNMENT

IN			1	14				VCC
										1		8		VCC
								IN
NC			2	13				NC		2		7		TAP 1
								TAP 2
NC			3	12				TAP 1		3
								TAP 4				6		TAP 3
TAP 2			4	11				NC		4		5
								GND						TAP 5
NC			5	10				TAP 3

TAP 4		6		9			NC	DS1000M-IND 8-PIN DIP
											(300 MIL)
			7	8
GND							TAP 5 See Mech. Drawings Section
DS1000-IND 14-PIN DIP
			(300 MIL)					IN			1	8		VCC
See Mech. Drawings Section								TAP 2			2	7		TAP 1
								TAP 4			3	6		TAP 3
								GND			4	5		TAP 5

DS1000Z-IND 8-PIN SOIC

(150 MIL)

See Mech. Drawings Section

PIN DESCRIPTION

TAP 1-TAP 5 - TAP Output Number

VCC	- +5 Volts
GND	- Ground
NC	- No Connection
IN	- Input

DESCRIPTION

The DS1000-IND series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These devices are offered in standard 8- and 14-pin DIPs that are pin-compatible with hybrid delay lines. Alternatively, 8-pin SOICs are available to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead configurations. The DS1000-IND series delay lines provide a nominal accuracy of ± 5% or

± 2 ns, whichever is greater. The DS1000-IND 5-Tap Silicon Delay Line reproduces the input logic state at the output after a fixed delay as specified by the extension of the part number after the dash. The DS1000-IND is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to ten 74LS loads.

Dallas Semiconductor can customize standard products to meet special needs. For special requests and rapid delivery, call [phone].

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DS1000-IND

LOGIC DIAGRAM Figure 1

DS1000-IND PART NUMBER DELAY TABLE Table 1

	PART #		TAP 1				TAP 2			TAP 3			TAP 4			TAP 5
			TOLERANCE				TOLERANCE			TOLERANCE			TOLERANCE			TOLERANCE
	DS1000-	Nom				Nom			Nom			Nom			Nom
			Init		T&V		Init	T&V		Init	T&V		Init	T&V		Init	T&V
	-20	4	2		2	8	2	2	12	2	2	16	2	2	20	2	2
	-25	5	2		2	10	2	2	15	2	2	20	2	2	25	2	2
	-30	6	2		2	12	2	2	18	2	2	24	2	2	30	2	2.4
	-35	7	2		2	14	2	2	21	2	2	28	2	2.2	35	2	2.8
	-40	8	2		2	16	2	2	24	2	2	32	2	2.6	40	2	3.2
	-45	9	2		2	18	2	2	27	2	2.2	36	2	2.9	45	2.3	3.6
	-50	10	2		2	20	2	2	30	2	2.4	40	2	3.2	50	2.5	4
	-60	12	2		2	24	2	2	36	2	2.9	48	2.4	3.9	60	3	4.8
	-75	15	2		2	30	2	2.4	45	2.3	3.6	60	3	4.8	75	3.8	6
	-100	20	2		2	40	2	3.2	60	3	4.8	80	4	6.4	100	5	8
	-125	25	2		2	50	2.5	4	75	3.8	6	100	5	8	125	6.3	10
	-150	30	2		2.4	60	3	4.8	90	4.5	7.2	120	6	9.6	150	7.5	12
	-175	35	2		2.8	70	3.5	5.6	105	5.3	8.4	140	7	11.2	175	8.8	14
	-200	40	2		3.2	80	4	6.4	120	6	9.6	160	8	12.8	200	10	16
	-250	50	2.5		4	100	5	8	150	7.5	12	200	10	16	250	12.5	20
	-500	100	5		8	200	10	16	300	15	24	400	20	32	500	25	40

NOTES:

1.Initial tolerances are ± with respect to the nominal value at 25° C and 5V.

2.Temperature tolerance is ± with respect to the initial delay value over a range of -40° C to 85° C, and a supply voltage range of 4.75 to 5.25V.

3.All tap delays tend to vary unidirectionally with temperature or voltage changes. For example, if TAP 1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.

4.Intermediate delay values and packaging variations are available on a custom basis. For further information, call (972) 371–4348.

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