DADD PPG33F-0.5, PPG33F-0.5C3, PPG33F-0.5M, PPG33F-0.5MC3, PPG33F-1, PPG33F-10, PPG33F-10C3, PPG33F-10M, PPG33F-10MC3, PPG33F-1M, PPG33F-1MC3, PPG33F-2, PPG33F-20, PPG33F-20C3, PPG33F-20M, PPG33F-20MC3, PPG33F-2C3, PPG33F-4, PPG33F-40, PPG33F-40C3, PPG33F-40M, PPG33F-40MC3, PPG33F-4C3, PPG33F-4M, PPG33F-4MC3, PPG33F-5, PPG33F-2M, PPG33F-2MC3, PPG33F-3, PPG33F-30, PPG33F-30C3, PPG33F-30M, PPG33F-30MC3, PPG33F-3C3, PPG33F-3M, PPG33F-3MC3, PPG33F-50, PPG33F-50C3, PPG33F-50M, PPG33F-50MC3, PPG33F-5C3, PPG33F-5M, PPG33F-5MC3, PPG33F-6, PPG33F-6C3, PPG33F-6M, PPG33F-6MC3, PPG33F-8, PPG33F-8C3, PPG33F-8M, PPG33F-8MC3 Datasheet

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Gull-Wing
PPG33F-xxC3 Commercial PPG33F-xxMC3 Military

 

 

 

 

PPG33F

 

 

 

 

 

 

3-BIT PROGRAMMABLE

 

data

 

 

®

 

3

PULSE GENERATOR

 

delay

 

(SERIES PPG33F)

 

devices, inc.

 

 

 

 

 

FEATURES

PACKAGES

 

 

Digitally programmable in 7 steps

Monotonic pulse-width-vs-address variation

Rising edge triggered

Two separate outputs: inverting & non-inverting

Precise and stable pulse width

Input & outputs fully TTL interfaced & buffered

10 T2L fan-out capability

Fits standard 14-pin DIP socket

Auto-insertable

 

 

 

 

 

TRIG

 

1

16

VCC

 

 

 

 

 

 

 

 

 

 

 

 

TRIG

 

1

14

VCC

OUT

 

2

15

OUT/

 

 

OUT

 

2

13

OUT/

N/C

 

3

14

N/C

 

 

 

 

N/C

 

3

12

N/C

N/C

 

4

13

N/C

 

 

 

 

N/C

 

4

11

N/C

N/C

 

5

12

N/C

 

 

 

 

N/C

 

5

10

A0

N/C

 

6

11

A0

 

 

 

 

RES

 

6

9

A1

RES

 

7

10

A1

 

 

 

 

GND

 

7

8

A2

 

 

9

A2

 

GND

 

8

 

 

DIP

PPG33F-xx Commercial

PPG33F-xxM Military

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PPG33F-series device is a 3-bit digitally programmable pulse

TRIG

Trigger Input

generator. The width, PWA, depends on the address code (A2-A0)

OUT

Non-inverted Output

according to the following formula:

OUT/

Inverted Output

 

A0-A2

Address Bits

PWA = PW0 + TINC * A

RES

Reset

 

VCC

+5 Volts

where A is the address code, TINC is the incremental pulse width of the

GND

Ground

device, and PW0 is the inherent pulse width of the device. The

incremental width is specified by the dash number of the device and can range from 0.5ns through 50ns, inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active.

SERIES SPECIFICATIONS

Programmed pulse width tolerance: 5% or 1ns,

whichever is greater

Inherent width (PW0): 9ns typical

Inherent delay (TTO): 3.5ns ± 2ns

Operating temperature: 0° to 70° C

Supply voltage VCC: 5VDC ± 5%

Supply current: ICC = 41ma typical

©1997 Data Delay Devices

DASH NUMBER SPECIFICATIONS

Part

Incremental Width

Total Width

Number

Per Step (ns)

Change (ns)

PPG33F-.5

0.5 ± 0.3

3.50 ± 1.00

PPG33F-1

1 ± 0.4

7.00 ± 1.00

PPG33F-2

2 ± 0.4

14.0 ± 1.00

PPG33F-3

3 ± 0.5

21.0 ± 1.05

PPG33F-4

4 ± 0.5

28.0 ± 1.40

PPG33F-5

5 ± 0.6

35.0 ± 1.75

PPG33F-6

6 ± 0.7

42.0 ± 2.10

PPG33F-8

8 ± 0.8

56.0 ± 2.80

PPG33F-10

10 ± 1.0

70.0 ± 3.50

PPG33F-20

20 ± 1.5

140 ± 7.00

PPG33F-30

30 ± 1.8

210 ± 10.5

PPG33F-40

40 ± 2.0

280 ± 14.0

PPG33F-50

50 ± 2.5

350 ± 17.5

NOTE: Any dash number between .5 and 50 not shown is also available.

Doc #97010

DATA DELAY DEVICES, INC.

1

1/15/97

3 Mt. Prospect Ave. Clifton, NJ 07013

DADD PPG33F-0.5, PPG33F-0.5C3, PPG33F-0.5M, PPG33F-0.5MC3, PPG33F-1, PPG33F-10, PPG33F-10C3, PPG33F-10M, PPG33F-10MC3, PPG33F-1M, PPG33F-1MC3, PPG33F-2, PPG33F-20, PPG33F-20C3, PPG33F-20M, PPG33F-20MC3, PPG33F-2C3, PPG33F-4, PPG33F-40, PPG33F-40C3, PPG33F-40M, PPG33F-40MC3, PPG33F-4C3, PPG33F-4M, PPG33F-4MC3, PPG33F-5, PPG33F-2M, PPG33F-2MC3, PPG33F-3, PPG33F-30, PPG33F-30C3, PPG33F-30M, PPG33F-30MC3, PPG33F-3C3, PPG33F-3M, PPG33F-3MC3, PPG33F-50, PPG33F-50C3, PPG33F-50M, PPG33F-50MC3, PPG33F-5C3, PPG33F-5M, PPG33F-5MC3, PPG33F-6, PPG33F-6C3, PPG33F-6M, PPG33F-6MC3, PPG33F-8, PPG33F-8C3, PPG33F-8M, PPG33F-8MC3 Datasheet

PPG33F

APPLICATION NOTES

DEVICE TIMING

The timing definitions and restrictions for the PPG33F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input. After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger.

At power-up, the state of the PPG33F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up.

POWER SUPPLY BYPASSING

The PPG33F relies on a stable power supply to produce repeatable pulses within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to each VCC pin, is recommended. A wide VCC trace should connect all VCC pins externally, and a clean ground plane should be used.

INCREMENT TOLERANCES

Please note that the increment tolerances listed represent a design goal. Although most increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

`A2-A0

A i

 

 

 

Ai+1

 

 

 

TRW

TOAX

TATS

RES

 

 

 

 

 

 

TRTS

TTW

 

 

 

TRIG

 

 

 

 

 

 

 

TTO

TRO

 

 

OUT

 

 

TOTR

 

 

 

 

 

 

 

 

TSKEW

 

PWA

 

OUT/

Figure 1: Timing Diagram

Doc #97010

DATA DELAY DEVICES, INC.

2

1/15/97

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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