Datadelay PPG312F-400C5, PPG312F-400M, PPG312F-400MC5, PPG312F-5, PPG312F-50 Datasheet

...
0 (0)
PIN DESCRIPTIONS
TRIG Trigger Input
OUT Non-inverted Output OUT/ Inverted Output A0-A11 Address Bits
RES Reset VCC +5 Volts GND Ground
PPG312F-xx DIP
PPG312F-xxC5 Gull-Wing
PPG312F-xxM Military DIP
PPG312F-xxMC5 Military Gull-Wing

 

 

 

PPG312F

 

 

 

 

 

12-BIT PROGRAMMABLE

data

 

 

®

 

3

PULSE GENERATOR

delay

 

(SERIES PPG312F)

devices, inc.

 

 

 

 

 

FEATURES

Digitally programmable in 4096 steps

Monotonic pulse-width-vs-address variation

Rising edge triggered

Two separate outputs: inverting & non-inverting

Precise and stable pulse width

Input & outputs fully TTL interfaced & buffered

10 T2L fan-out capability

Fits standard 40-pin DIP socket

Auto-insertable

 

 

 

 

PACKAGES

 

 

 

 

 

TRIG

 

1

40

VCC

 

 

 

 

 

N/C

 

2

39

N/C

 

 

 

 

 

N/C

 

3

38

OUT

 

N/C

 

4

37

OUT/

 

 

N/C

 

5

36

N/C

 

 

N/C

 

6

35

RES

 

 

N/C

 

7

34

N/C

 

GND

 

8

33

N/C

 

N/C

 

9

32

VCC

 

N/C

 

10

31

A0

 

GND

 

11

30

A1

 

A3

 

12

29

A2

 

A5

 

13

28

N/C

 

A6

 

14

27

N/C

 

A7

 

15

26

N/C

 

GND

 

16

25

N/C

 

A8

 

17

24

N/C

 

A9

 

18

23

A4

 

A10

 

19

22

N/C

 

A11

 

20

21

VCC

 

 

 

 

 

 

FUNCTIONAL DESCRIPTION

The PPG312F-series device is a 12-bit digitally programmable pulse generator. The width, PWA, depends on the address code (A11-A0) according to the following formula:

PWA = PW0 + TINC * A

where A is the address code, TINC is the incremental pulse width of the device, and PW0 is the inherent pulse width of the device. The

incremental width is specified by the dash number of the device and can range from 0.5ns through 400ns, inclusively. RESET is held LOW during normal operation. When it is brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively, and the unit is ready for the next trigger input. The address is not latched and must remain asserted while the output pulse is active.

SERIES SPECIFICATIONS

Programmed pulse width tolerance: 5% or 2ns,

whichever is greater

Inherent width (PW0): 20ns typical

Inherent delay (TTO): 10ns ± 2ns

Operating temperature: 0° to 70° C

Supply voltage VCC: 5VDC ± 5%

Supply current: ICC = 200ma typical

DASH NUMBER SPECIFICATIONS

Part

Incremental Width

Total Width

Number

Per Step (ns)

Change (us)

PPG312F-.5

.5 ± .3

2.048 ± 0.10

PPG312F-1

1

± .5

4.096 ± 0.20

PPG312F-2

2

± .5

8.192 ± 0.41

PPG312F-5

5 ± 1.5

20.48 ± 1.02

PPG312F-10

10

± 2.0

40.96 ± 2.05

PPG312F-20

20

± 2.0

81.92 ± 4.10

PPG312F-50

50

± 2.5

204.8 ± 10.2

PPG312F-100

100 ± 5.0

409.6 ± 20.5

PPG312F-200

200

± 10.0

819.2 ± 41.0

PPG312F-400

400

± 20.0

1,638.4 ± 81.9

NOTE: Any dash number between .5 and 400 not shown is also available.

©1997 Data Delay Devices

Doc #97008

DATA DELAY DEVICES, INC.

1

1/15/97

3 Mt. Prospect Ave. Clifton, NJ 07013

Datadelay PPG312F-400C5, PPG312F-400M, PPG312F-400MC5, PPG312F-5, PPG312F-50 Datasheet

PPG312F

APPLICATION NOTES

DEVICE TIMING

The timing definitions and restrictions for the PPG312F are shown in Figure 1. The unit is activated by a rising edge on the TRIG input.

After a time, TTO (called the inherent delay), the rising edge of the pulse appears at OUT. The duration of the pulse is given by the above equation. For the duration of the pulse, the device ignores subsequent triggers. Once the falling edge of the pulse has appeared at OUT, an additional time, TOTR, is required before the device can respond to the next trigger.

At power-up, the state of the PPG312F is unknown. Consequently, after power is applied, the unit may not respond to input triggers for a time equal to the maximum pulse width, PWT. After this time, the unit will function properly. If your application requires that the device function immediately, issue a quick reset at power-up.

POWER SUPPLY BYPASSING

The PPG312F relies on a stable power supply to produce repeatable pulses within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to each VCC pin, is recommended. A wide VCC trace should connect all VCC pins externally, and a clean ground plane should be used.

INCREMENT TOLERANCES

Please note that the increment tolerances listed represent a design goal. Although most increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

`A11-A0

A i

 

 

 

Ai+1

 

 

 

TRW

TOAX

TATS

RES

 

 

 

 

 

 

TRTS

TTW

 

 

 

TRIG

 

 

 

 

 

 

 

TTO

TRO

 

 

OUT

 

 

TOTR

 

 

 

 

 

 

 

 

TSKEW

 

PWA

 

OUT/

 

 

 

 

 

 

 

 

Figure 1: Timing Diagram

 

Doc #97008

DATA DELAY DEVICES, INC.

2

1/15/97

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

Loading...
+ 3 hidden pages