Datadelay PDU54-100, PDU54-1000, PDU54-1000C4, PDU54-1000M, PDU54-1000MC4 Datasheet

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PDU54

4-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU54)

data 3 ® delay

devices, inc.

FEATURES

PACKAGES

Digitally programmable in 16 delay steps

Monotonic delay-versus-address variation

Precise and stable delays

Input & outputs fully 100K-ECL interfaced & buffered

Available in 24-pin DIP (600 mil) socket or SMD

PDU54-xx DIP

PDU54-xxM Military DIP

N/C

 

1

24

 

IN

N/C

1

24

IN

N/C

 

2

23

 

N/C

N/C

2

23

N/C

 

 

 

 

GND

3

22

VEE

GND

 

3

22

 

VEE

 

 

N/C

4

21

A3

 

 

N/C

 

4

21

 

A3

 

 

N/C

5

20

N/C

 

 

N/C

 

5

20

 

N/C

N/C

6

19

N/C

 

 

N/C

 

6

19

 

N/C

N/C

7

18

A2

 

 

N/C

 

7

18

 

A2

N/C

8

17

A1

 

 

GND

9

16

VEE

N/C

 

8

17

 

A1

 

 

OUT

10

15

A0

 

 

 

 

 

GND

 

9

16

 

VEE

N/C

11

14

N/C

 

 

OUT

 

10

15

 

A0

N/C

12

13

N/C

N/C

 

11

14

 

N/C

PDU54-xxC4

 

SMD

 

 

 

N/C

 

12

13

 

N/C

PDU54-xxMC4 Mil SMD

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU54-series device is a 4-bit digitally programmable delay line. The delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the address code (A3-A0) according to the following formula:

TDA = TD0 + TINC * A

IN

Signal Input

OUT

Signal Output

A3-A0

Address Bits

VEE

-5 Volts

GND

Ground

where A is the address code, TINC is the incremental delay of the device, and TD0 is the inherent delay of the device. The incremental delay is specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

Total programmed delay tolerance: 5% or 40ps,

whichever is greater

Inherent delay (TD0): 3.3ns typical

Address to input setup (TAIS): 2.9ns

Operating temperature: 0° to 85° C

Temperature coefficient: 100PPM/°C (excludes TD0)

Supply voltage VEE: -5VDC ± 0.7V

Power Supply Current: -300ma typical (50Ω to -2V)

Minimum pulse width: 3ns or 10% of total delay,

whichever is greater

Minimum period: 8ns or 2 x pulse width, whichever

 

 

 

 

 

 

 

 

 

 

 

 

is greater

 

 

 

 

 

 

 

 

 

 

 

 

 

A3-A0

 

A i-1

 

 

 

 

 

 

 

 

Ai

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWIN

 

 

 

TOAX

 

 

 

TAIS

 

 

 

 

 

 

 

 

 

 

 

IN

TDA PWOUT

OUT

Figure 1: Timing Diagram

©1997 Data Delay Devices

DASH NUMBER SPECIFICATIONS

Part

Incremental Delay

Total Delay

Number

Per Step (ps)

Change (ns)

PDU54-100

100

± 50

1.50

PDU54-200

200

± 60

3.00

PDU54-250

250

± 60

3.75

PDU54-400

400

± 80

6.00

PDU54-500

500 ± 100

7.50

PDU54-750

750 ± 100

11.25

PDU54-1000

1000

± 200

15.00

PDU54-1200

1200

± 200

18.00

PDU54-1500

1500

± 200

22.50

PDU54-2000

2000

± 400

30.00

PDU54-2500

2500

± 400

37.50

PDU54-3000

3000

± 500

45.00

NOTE: Any dash number between 100 and 3000 not shown is also available.

Doc #98004

DATA DELAY DEVICES, INC.

1

3/18/98

3 Mt. Prospect Ave. Clifton, NJ 07013

Datadelay PDU54-100, PDU54-1000, PDU54-1000C4, PDU54-1000M, PDU54-1000MC4 Datasheet

PDU54

APPLICATION NOTES

ADDRESS UPDATE

The PDU54 is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.

After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended

conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.

When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.

Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

PACKAGE DIMENSIONS

24 23 22 21 20 19 18 17 16 15 14 13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.600

.580

 

 

 

 

±.005

MAX.

 

 

 

 

 

 

 

 

 

 

 

 

.010

 

 

 

 

 

 

 

 

±.002

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

12

1.270±.010

.380

MAX.

Lead Material: Nickel-Iron alloy 42 TIN PLATE

 

.015 TYP.

.018 TYP.

.070 MAX.

 

1.100±.010 11 Equal spaces

each .100±.010 Non-Accumulative

PDU54-xx (Commercial DIP)

PDU54-xxM (Military DIP)

Doc #98004

DATA DELAY DEVICES, INC.

2

3/18/98

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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