Datadelay PDU53-1000C3, PDU53-1000M, PDU53-1000MC3, PDU53-100C3, PDU53-100M Datasheet

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PDU53-xxC3 SMD PDU53-xxMC3 Mil SMD

PDU53

3-BIT, ECL-INTERFACED PROGRAMMABLE DELAY LINE (SERIES PDU53)

data 3 ® delay

devices, inc.

FEATURES

Digitally programmable in 8 delay steps

Monotonic delay-versus-address variation

Precise and stable delays

Input & outputs fully 100K-ECL interfaced & buffered

Available in 16-pin DIP (600 mil) socket or SMD

PACKAGES

N/C

 

1

16

 

IN

 

 

 

 

 

 

 

 

N/C

 

1

16

 

IN

N/C

 

 

2

15

 

A2

N/C

 

2

15

 

A2

 

 

 

 

 

GND

 

3

14

 

A1

GND

 

3

14

 

A1

 

 

OUT

 

4

13

 

VEE

 

 

 

 

 

 

 

 

 

OUT

 

 

4

13

 

VEE

N/C

 

5

12

 

A0

N/C

 

 

5

12

 

A0

N/C

 

6

11

 

N/C

N/C

 

6

11

 

N/C

N/C

 

7

10

 

N/C

 

 

 

 

 

 

N/C

 

8

9

 

N/C

 

 

 

 

N/C

 

 

7

10

 

N/C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/C

 

 

8

9

 

N/C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDU53-xx DIP

PDU53-xxM Military DIP

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU53-series device is a 3-bit digitally programmable delay line.

IN

Signal Input

The delay, TDA, from the input pin (IN) to the output pin (OUT) depends

OUT

Signal Output

on the address code (A2-A0) according to the following formula:

A2

Address Bit 2

 

A1

Address Bit 1

TDA = TD0 + TINC * A

A0

Address Bit 0

 

VEE

-5 Volts

where A is the address code, TINC is the incremental delay of the device,

GND

Ground

and TD0 is the inherent delay of the device. The incremental delay is

specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

Total programmed delay tolerance: 5% or 40ps,

whichever is greater

Inherent delay (TD0): 2.2ns typical

Address to input setup (TAIS): 2.9ns

Operating temperature: 0° to 85° C

Temperature coefficient: 100PPM/°C (excludes TD0)

Supply voltage VEE: -5VDC ± 0.7V

Power Supply Current: -150ma typical (50Ω to -2V)

Minimum pulse width: 3ns or 15% of total delay,

whichever is greater

Minimum period: 8ns or 2 x pulse width, whichever

 

 

 

 

 

 

 

 

 

 

 

 

is greater

 

 

 

 

 

 

 

 

 

 

 

 

 

A2-A0

 

A i-1

 

 

 

 

 

 

 

 

Ai

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PWIN

 

 

 

TOAX

 

 

 

TAIS

 

 

 

 

 

 

 

 

 

 

 

IN

TDA PWOUT

OUT

Figure 1: Timing Diagram

©1997 Data Delay Devices

DASH NUMBER SPECIFICATIONS

Part

Incremental Delay

Total Delay

Number

Per Step (ps)

Change (ns)

PDU53-100

100

± 50

0.70

PDU53-200

200

± 60

1.40

PDU53-250

250

± 60

1.75

PDU53-400

400

± 80

2.80

PDU53-500

500 ± 100

3.50

PDU53-750

750 ± 100

5.25

PDU53-1000

1000

± 200

7.00

PDU53-1200

1200

± 200

8.40

PDU53-1500

1500

± 200

10.50

PDU53-2000

2000

± 400

14.00

PDU53-2500

2500

± 400

17.50

PDU53-3000

3000

± 500

21.00

NOTE: Any dash number between 100 and 3000 not shown is also available.

Doc #98003

DATA DELAY DEVICES, INC.

1

3/18/98

3 Mt. Prospect Ave. Clifton, NJ 07013

Datadelay PDU53-1000C3, PDU53-1000M, PDU53-1000MC3, PDU53-100C3, PDU53-100M Datasheet

PDU53

APPLICATION NOTES

ADDRESS UPDATE

The PDU53 is a memory device. As such, special precautions must be taken when changing the delay address in order to prevent spurious output signals. The timing restrictions are shown in Figure 1.

After the last signal edge to be delayed has appeared on the OUT pin, a minimum time, TOAX, is required before the address lines can change. This time is given by the following relation:

TOAX = max { (Ai - A i-1) * TINC , 0 }

where A i-1 and Ai are the old and new address codes, respectively. Violation of this constraint may, depending on the history of the input signal, cause spurious signals to appear on the OUT pin. The possibility of spurious signals persists until the required TOAX has elapsed.

INPUT RESTRICTIONS

There are three types of restrictions on input pulse width and period listed in the AC Characteristics table. The recommended

conditions are those for which the delay tolerance specifications and monotonicity are guaranteed. The suggested conditions are those for which signals will propagate through the unit without significant distortion. The absolute conditions are those for which the unit will produce some type of output for a given input.

When operating the unit between the recommended and absolute conditions, the delays may deviate from their values at low frequency. However, these deviations will remain constant from pulse to pulse if the input pulse width and period remain fixed. In other words, the delay of the unit exhibits frequency and pulse width dependence when operated beyond the recommended conditions. Please consult the technical staff at Data Delay Devices if your application has specific high-frequency requirements.

Please note that the increment tolerances listed represent a design goal. Although most delay increments will fall within tolerance, they are not guaranteed throughout the address range of the unit. Monotonicity is, however, guaranteed over all addresses.

PACKAGE DIMENSIONS

16

15

14

13

12

11

10

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

.600

.580

 

 

 

 

±.005

MAX.

 

 

 

 

 

 

 

 

 

 

 

 

.010

 

 

 

 

 

 

 

 

±.002

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

.870±.010

 

.380

 

MAX.

 

.015 TYP.

.018

.070 MAX.

TYP.

.700±.010

 

 

7 Equal spaces

 

each .100±.010

 

Non-Accumulative

Lead Material: Nickel-Iron alloy 42 TIN PLATE

PDU53-xx (Commercial DIP)

PDU53-xxM (Military DIP)

Doc #98003

DATA DELAY DEVICES, INC.

2

3/18/98

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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