Datadelay PDU17F-1MC5, PDU17F-2, PDU17F-2C5, PDU17F-2M, PDU17F-2MC5 Datasheet

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PDU17F

 

 

 

 

 

7-BIT PROGRAMMABLE

data

 

 

®

 

3

DELAY LINE

delay

 

(SERIES PDU17F)

devices, inc.

 

 

 

 

 

FEATURES

Digitally programmable in 128 delay steps

Monotonic delay-versus-address variation

Two separate outputs: inverting & non-inverting

Precise and stable delays

Input & outputs fully TTL interfaced & buffered

10 T2L fan-out capability

Fits standard 40-pin DIP socket

Auto-insertable

 

 

 

 

PACKAGES

 

 

 

 

 

 

N/C

 

1

40

VCC

 

 

 

 

 

 

 

 

OUT/

 

2

39

N/C

 

 

 

 

 

 

 

 

OUT

 

3

38

A0

 

 

 

EN/

 

4

37

A1

PDU17F-xx

 

 

GND

 

5

36

A2

 

DIP

N/C

 

6

35

VCC

 

N/C

 

7

34

N/C

PDU17F-xxC5

 

 

N/C

 

8

33

A3

Gull-Wing

 

GND

 

9

32

A4

PDU17F-xxM

N/C

 

10

31

A5

 

Military DIP

N/C

 

11

30

VCC

 

N/C

 

12

29

N/C

PDU17F-xxMC5

 

N/C

 

13

28

N/C

Military Gull-Wing

 

 

GND

 

14

27

N/C

 

 

 

N/C

 

15

26

N/C

 

 

 

EN/

 

16

25

VCC

 

 

 

N/C

 

17

24

N/C

 

 

 

IN

 

18

23

A6

 

 

 

N/C

 

19

22

N/C

 

 

 

GND

 

20

21

N/C

 

 

 

 

 

 

 

 

 

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The PDU17F-series device is a 7-bit digitally programmable delay line.

IN

Delay Line Input

The delay, TDA, from the input pin (IN) to the output pins (OUT, OUT/)

OUT

Non-inverted Output

depends on the address code (A6-A0) according to the following formula:

OUT/

Inverted Output

 

A0-A6

Address Bits

TDA = TD0 + TINC * A

EN/

Output Enable

 

VCC

+5 Volts

where A is the address code, TINC is the incremental delay of the device,

GND

Ground

and TD0 is the inherent delay of the device. The incremental delay is

specified by the dash number of the device and can range from 0.5ns through 10ns, inclusively. The enable pins (EN/) are held LOW during normal operation. These pins must always be in the same state and may be tied together externally. When these signals are brought HIGH, OUT and OUT/ are forced into LOW and HIGH states, respectively. The address is not latched and must remain asserted during normal operation.

SERIES SPECIFICATIONS

Programmed delay tolerance: 5% or 2ns,

whichever is greater

Inherent delay (TD0): 13ns typical (OUT)

12ns typical (OUT/)

Setup time and propagation delay: Address to input setup (TAIS): 10ns

Disable to output delay (TDISO): 6ns typ. (OUT)

Operating temperature: 0° to 70° C

Temperature coefficient: 100PPM/°C (excludes TD0)

Supply voltage VCC: 5VDC ± 5%

Supply current: ICCH = 68ma

ICCL = 86ma

Minimum pulse width: 8% of total delay

DASH NUMBER SPECIFICATIONS

Part

Incremental Delay

Total Delay

Number

Per Step (ns)

Change (ns)

PDU17F-.5

.5 ± .3

63.5

± 3.2

PDU17F-1

1

± .5

127 ± 6.4

PDU17F-2

2

± .5

254 ± 12.7

PDU17F-3

3 ± 1.0

381 ± 19.1

PDU17F-4

4 ± 1.0

508 ± 25.4

PDU17F-5

5 ± 1.5

635 ± 31.8

PDU17F-6

6 ± 1.5

762 ± 38.1

PDU17F-8

8 ± 2.0

1,016

± 50.8

PDU17F-10

10

± 2.0

1,270

± 63.5

NOTE: Any dash number between .5 and 10 not shown is also available.

©1997 Data Delay Devices

Doc #97005

DATA DELAY DEVICES, INC.

1

1/14/97

3 Mt. Prospect Ave. Clifton, NJ 07013

Datadelay PDU17F-1MC5, PDU17F-2, PDU17F-2C5, PDU17F-2M, PDU17F-2MC5 Datasheet

PDU17F

APPLICATION NOTES

ADDRESS UPDATE

possibility of spurious signals persists until the

 

required TDISH has elapsed.

The PDU17F is a memory device. As such,

INPUT RESTRICTIONS

special precautions must be taken when

changing the delay address in order to prevent

 

spurious output signals. The timing restrictions

There are three types of restrictions on input

are shown in Figure 1.

pulse width and period listed in the AC

After the last signal edge to be delayed has

Characteristics table. The recommended

conditions are those for which the delay

appeared on the OUT pin, a minimum time,

tolerance specifications and monotonicity are

TOAX, is required before the address lines can

guaranteed. The suggested conditions are

change. This time is given by the following

those for which signals will propagate through the

relation:

unit without significant distortion. The absolute

TOAX = max { (Ai - A i-1) * TINC , 0 }

conditions are those for which the unit will

produce some type of output for a given input.

where A i-1 and Ai are the old and new address

When operating the unit between the

codes, respectively. Violation of this constraint

recommended and absolute conditions, the

may, depending on the history of the input signal,

delays may deviate from their values at low

cause spurious signals to appear on the OUT

frequency. However, these deviations will

pin. The possibility of spurious signals persists

remain constant from pulse to pulse if the input

until the required TOAX has elapsed.

pulse width and period remain fixed. In other

A similar situation occurs when using the EN/

words, the delay of the unit exhibits frequency

and pulse width dependence when operated

signal to disable the output while IN is active. In

beyond the recommended conditions. Please

this case, the unit must be held in the disabled

consult the technical staff at Data Delay Devices

state until the device is able to “clear” itself. This

if your application has specific high-frequency

is achieved by holding the EN/ signal high and

requirements.

the IN signal low for a time given by:

 

TDISH = Ai * TINC

Please note that the increment tolerances listed

represent a design goal. Although most delay

Violation of this constraint may, depending on

increments will fall within tolerance, they are not

guaranteed throughout the address range of the

the history of the input signal, cause spurious

unit. Monotonicity is, however, guaranteed over

signals to appear on the OUT pin. The

all addresses.

A6-A0

A i-1

 

Ai

TAENS

 

TOAX

TAIS

EN/

 

 

 

TENIS

PWIN

 

TDISH

IN

 

 

 

TDA

PWOUT

 

TDISO

OUT

TSKEW

OUT/

Figure 1: Timing Diagram

Doc #97005

DATA DELAY DEVICES, INC.

2

1/14/97

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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