TTL-INTERFACED, GATED DELAY LINE OSCILLATOR (SERIES DLO31F)
DLO31F
data 3 ® delay
devices, inc.
FEATURES
∙Continuous or keyable wave train
∙Synchronizes with arbitrary gating signal
∙Fits standard 14-pin DIP socket
∙Low profile
∙Auto-insertable
∙Input & outputs fully TTL interfaced & buffered
∙Available in frequencies from 2MHz to 40MHz
PACKAGES
C1 |
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1 |
14 |
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VCC |
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C1 |
1 |
14 |
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VCC |
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N/C |
2 |
13 |
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N/C |
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N/C |
3 |
12 |
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N/C |
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N/C |
4 |
11 |
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N/C |
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N/C |
5 |
10 |
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C2 |
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10 |
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C2 |
N/C |
6 |
9 |
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N/C |
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GND |
7 |
8 |
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GB |
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GND |
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7 |
8 |
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GB |
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DLO31F-xx |
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DIP |
Military SMD |
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DLO31F-xxA2 |
Gull-Wing |
DLO31F-xxMD1 |
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DLO31F-xxB2 |
J-Lead |
DLO31F-xxMD4 |
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DLO31F-xxM |
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Military DIP |
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FUNCTIONAL DESCRIPTION
The DLO31F-series device is a gated delay line oscillator. The device produces a stable square wave which is synchronized with the falling edge of the Gate Input (GB). The frequency of oscillation is given by the device dash number (See Table). The two outputs (C1,C2) are in phase during oscillation, but return to opposite logic levels when the device is disabled.
PIN DESCRIPTIONS
GB |
Gate Input |
C1 |
Clock Output 1 |
C2 |
Clock Output 2 |
VCC |
+5 Volts |
GND |
Ground |
SERIES SPECIFICATIONS |
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DASH NUMBER |
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∙ |
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Frequency accuracy: |
2% |
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SPECIFICATIONS |
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∙ |
Inherent delay (TE0): |
5.5ns typical |
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Frequency |
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∙ |
Output skew: |
3.5ns typical |
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Number |
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Output rise/fall time: |
2ns typical |
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DLO31F-2 |
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2.0 ± 0.04 |
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∙ |
Supply voltage: |
5VDC ± 5% |
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DLO31F-2.5 |
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2.5 ± 0.05 |
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∙ |
Supply current: |
40ma typical (7ma when disabled) |
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DLO31F-3 |
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3.0 |
± 0.06 |
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∙ |
Operating temperature: |
0° to 70° C |
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DLO31F-3.5 |
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3.5 |
± 0.07 |
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DLO31F-4 |
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4.0 ± 0.08 |
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∙ |
Temperature coefficient: 100 PPM/°C (See text) |
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DLO31F-4.5 |
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4.5 ± 0.09 |
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DLO31F-5 |
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5.0 |
± 0.10 |
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DLO31F-5.5 |
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5.5 |
± 0.11 |
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DLO31F-6 |
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6.0 |
± 0.12 |
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DLO31F-7 |
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7.0 |
± 0.14 |
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GATE |
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DLO31F-8 |
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8.0 |
± 0.16 |
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(GB) |
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tEO |
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tGR |
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tDO |
DLO31F-9 |
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9.0 |
± 0.18 |
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DLO31F-10 |
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10 |
± 0.20 |
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CLOCK 1 |
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DLO31F-12 |
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12 |
± 0.24 |
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(C1) |
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tCS |
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DLO31F-14 |
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14 |
± 0.28 |
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CLOCK 2 |
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1/f0 |
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DLO31F-15 |
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15 |
± 0.30 |
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DLO31F-20 |
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20 |
± 0.40 |
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DLO31F-25 |
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25 |
± 0.50 |
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Figure 1: Timing Diagram |
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DLO31F-30 |
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30 |
± 0.60 |
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DLO31F-35 |
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35 |
± 0.70 |
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DLO31F-40 |
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40 |
± 0.80 |
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©1998 Data Delay Devices |
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NOTE: Any dash number |
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between 2 and 40 not shown |
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is also available. |
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Doc #98001 |
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DATA DELAY DEVICES, INC. |
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1 |
3/17/98 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
DLO31F
APPLICATION NOTES
THERMAL STABILITY
The delay line used internally to develop the clock signals in the DLO31F has a thermal coefficient of 100ppm/C. For low frequency units, this is also the thermal coefficient of the output frequency. For higher frequency units, however, other internal effects must be considered, and the actual thermal coefficient may be somewhat higher.
POWER SUPPLY BYPASSING
The DLO31F relies on a stable power supply to produce a repeatable frequency within the stated tolerances. A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended. A wide VCC trace and a clean ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER |
SYMBOL |
MIN |
MAX |
UNITS |
NOTES |
DC Supply Voltage |
VCC |
-0.3 |
7.0 |
V |
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Input Pin Voltage |
VIN |
-0.3 |
VDD+0.3 |
V |
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Storage Temperature |
TSTRG |
-55 |
150 |
C |
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Lead Temperature |
TLEAD |
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300 |
C |
10 sec |
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
NOTES |
High Level Output Voltage |
VOH |
2.5 |
3.4 |
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V |
VCC = MIN, IOH = MAX |
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VIH = MIN, VIL = MAX |
Low Level Output Voltage |
VOL |
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0.35 |
0.5 |
V |
VCC = MIN, IOL = MAX |
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VIH = MIN, VIL = MAX |
High Level Output Current |
IOH |
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-1.0 |
mA |
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Low Level Output Current |
IOL |
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20.0 |
mA |
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High Level Input Voltage |
VIH |
2.0 |
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V |
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Low Level Input Voltage |
VIL |
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0.8 |
V |
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Input Clamp Voltage |
VIK |
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-1.2 |
V |
VCC = MIN, II = IIK |
Input Current at Maximum |
IIHH |
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0.1 |
mA |
VCC = MAX, VI = 7.0V |
Input Voltage |
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High Level Input Current |
IIH |
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20 |
μA |
VCC = MAX, VI = 2.7V |
Low Level Input Current |
IIL |
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-0.6 |
mA |
VCC = MAX, VI = 0.5V |
Short-circuit Output Current |
IOS |
-60 |
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-150 |
mA |
VCC = MAX |
Output High Fan-out |
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25 |
Unit |
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Output Low Fan-out |
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12.5 |
Load |
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TABLE 3: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
Enable to Clock On (Inherent Delay) |
tEO |
3.5 |
5.5 |
7.0 |
ns |
Disable to Clock Off |
tDO |
3.5 |
5.5 |
7.0 |
ns |
Clock Skew |
tCS |
2.5 |
3.5 |
4.5 |
ns |
Gate Recovery Time |
tGR |
50 |
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% of Clock Period |
Doc #98001 DATA DELAY DEVICES, INC. 2
3/17/98 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |