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DDU8C3 |
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5-TAP, 3.3V CMOS-INTERFACED |
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data |
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® |
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3 |
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FIXED DELAY LINE |
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delay |
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(SERIES DDU8C3) |
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devices, inc. |
FEATURES
∙Five equally spaced outputs
∙Fits standard 8-pin DIP socket
∙Low profile
∙Auto-insertable
∙Input & outputs fully CMOS interfaced & buffered
∙10 T2L fan-out capability
PACKAGES
IN |
1 |
8 |
VDD |
T2 |
2 |
7 |
T1 |
T4 |
3 |
6 |
T3 |
GND |
4 |
5 |
T5 |
DDU8C3-xx DIP
DDU8C3-xxA1 Gull-Wing
FUNCTIONAL DESCRIPTION |
PIN DESCRIPTIONS |
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The DDU8C3-series device is a 5-tap digitally buffered delay line. The |
IN |
Signal Input |
signal input (IN) is reproduced at the outputs (T1-T5), shifted in time by an |
T1-T5 |
Tap Outputs |
amount determined by the device dash number (See Table). For dash |
VDD |
+3.3 Volts |
numbers 5020 and above, the total delay of the line is measured from IN to |
GND |
Ground |
T5, and the nominal tap-to-tap delay increment is given by one-fifth of the |
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total delay. For dash numbers below 5020, the total delay is measured from T1 to T5, and the delay increment is given by one-fourth of the total delay.
SERIES SPECIFICATIONS
∙Minimum input pulse width: 40% of total delay
∙Output rise time: 2ns typical
∙Supply voltage: 3.3VDC ± 0.3V
∙Supply current: ICCL = 40μa typical
ICCH = 7ma typical
∙Operating temperature: -40° to 85° C
∙Temp. coefficient of total delay: 300 PPM/°C
3.0ns 25% 25% 25% 25%
VDD IN |
T1 |
T2 |
T3 |
T4 |
T5 GND |
Functional diagram for dash numbers < 5020
20% 20% 20% 20% 20%
VDD IN |
T1 |
T2 |
T3 |
T4 |
T5 GND |
Functional diagram for dash numbers >= 5020
DASH NUMBER SPECIFICATIONS
Part |
Total |
Delay Per |
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Number |
Delay (ns) |
Tap (ns) |
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DDU8C3-5004 |
4 |
± 1.0 * |
1.0 ± 0.5 |
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DDU8C3-5006 |
6 |
± 1.0 * |
1.5 ± 0.5 |
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DDU8C3-5008 |
8 |
± 2.0 * |
2.0 ± 1.0 |
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DDU8C3-5010 |
10 |
± 2.0 * |
2.5 ± 1.0 |
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DDU8C3-5012 |
12 |
± 2.0 * |
3.0 ± 1.0 |
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DDU8C3-5014 |
14 |
± 2.0 * |
3.5 ± 1.0 |
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DDU8C3-5020 |
20 |
± 2.0 |
4.0 ± 1.0 |
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DDU8C3-5025 |
25 |
± 2.0 |
5.0 ± 1.5 |
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DDU8C3-5030 |
30 |
± 2.0 |
6.0 ± 1.5 |
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DDU8C3-5035 |
35 |
± 2.0 |
7.0 ± 1.8 |
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DDU8C3-5040 |
40 |
± 2.0 |
8.0 ± 2.0 |
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DDU8C3-5045 |
45 ± 2.25 |
9.0 ± 2.0 |
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DDU8C3-5050 |
50 |
± 2.5 |
10.0 ± 2.0 |
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DDU8C3-5060 |
60 |
± 3.0 |
12.0 ± 2.0 |
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DDU8C3-5075 |
75 ± 3.75 |
15.0 ± 2.5 |
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DDU8C3-5100 |
100 |
± 5.0 |
20.0 ± 3.0 |
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DDU8C3-5125 |
125 |
± 6.5 |
25.0 ± 3.0 |
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DDU8C3-5150 |
150 |
± 7.5 |
30.0 ± 3.0 |
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DDU8C3-5175 |
175 |
± 8.0 |
35.0 ± 4.0 |
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DDU8C3-5200 |
200 |
± 10.0 |
40.0 ± 4.0 |
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DDU8C3-5250 |
250 |
± 12.5 |
50.0 ± 5.0 |
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*Total delay is referenced to first tap output Input to first tap = 3.0ns ± 1ns
NOTE: Any dash number between 5004 and 5250 not shown is also available.
©2000 Data Delay Devices
Doc #00115 |
DATA DELAY DEVICES, INC. |
1 |
5/19/00 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
DDU8C3
APPLICATION NOTES
HIGH FREQUENCY RESPONSE
The DDU8C3 tolerances are guaranteed for input pulse widths and periods greater than those specified in the test conditions. Although the device will function properly for pulse widths as small as 40% of the total delay and periods as small as 80% of the total delay (for a symmetric input), the delays may deviate from their values at low frequency. However, for a given input condition, the deviation will be repeatable from pulse to pulse. Contact technical support at Data
Delay Devices if your application requires device testing at a specific input condition.
POWER SUPPLY BYPASSING
The DDU8C3 relies on a stable power supply to produce repeatable delays within the stated tolerances. A 0.1uf capacitor from VDD to GND, located as close as possible to the VDD pin, is recommended. A wide VDD trace and a clean ground plane should be used.
DEVICE SPECIFICATIONS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
PARAMETER |
SYMBOL |
MIN |
MAX |
UNITS |
NOTES |
DC Supply Voltage |
VDD |
-0.3 |
7.0 |
V |
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Input Pin Voltage |
VIN |
-0.3 |
VDD+0.3 |
V |
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Storage Temperature |
TSTRG |
-55 |
150 |
C |
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Lead Temperature |
TLEAD |
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300 |
C |
10 sec |
TABLE 2: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 3.00V to 3.60V)
PARAMETER |
SYMBOL |
MIN |
TYP |
MAX |
UNITS |
NOTES |
High Level Output Voltage |
VOH |
3.00 |
3.20 |
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V |
VDD = 3.3, IOH = MAX |
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VIH = MIN, VIL = MAX |
Low Level Output Voltage |
VOL |
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0.10 |
0.30 |
V |
VDD = 3.3, IOL = MAX |
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VIH = MIN, VIL = MAX |
High Level Output Current |
IOH |
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-24.0 |
mA |
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Low Level Output Current |
IOL |
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24.0 |
mA |
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High Level Input Voltage |
VIH |
2.50 |
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V |
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Low Level Input Voltage |
VIL |
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0.80 |
V |
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Input Current |
IIH |
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0.10 |
μA |
VDD = 3.3 |
Doc #00115 |
DATA DELAY DEVICES, INC. |
2 |
5/19/00 |
Tel: 973-773-2299 Fax: 973-773-9672 www.datadelay.com |