DADD 3D7501Z, 3D7501M, 3D7501H, 3D7501G, 3D7501 Datasheet

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		3D7501

MONOLITHIC MANCHESTER	data		®
MONOLITHIC MANCHESTER	data	3	®
ENCODER	delay	3
(SERIES 3D7501)	devices, inc.

FEATURES

∙All-silicon, low-power CMOS technology

∙TTL/CMOS compatible inputs and outputs

∙Vapor phase, IR and wave solderable

∙Auto-insertable (DIP pkg.)

∙Low ground bounce noise

∙Maximum data rate: 50 MBaud

PACKAGES

CLK	1	8	VDD
RESB	2	7	N/C
DAT	3	6	TXB
GND	4	5	TX

3D7501M	DIP (.300)
3D7501H	Gull Wing (.300)
3D7501Z	SOIC (.150)

CLK	1	14	VDD



N/C	2	13	N/C
N/C	3	12	N/C

RESB	4	11	N/C

DAT	5	10	N/C

N/C	6	9	TXB

GND	7	8	TX


3D7501	DIP (.300)
3D7501G	Gull Wing (.300)
3D7501D	SOIC (.150)

FUNCTIONAL DESCRIPTION

The 3D7501 is a monolithic CMOS Manchester Encoder. The clock and data, present at the unit input, are combined into a single bi- phase-level signal. In this encoding mode, a logic one is represented by a high-to-low transition within the bit cell, while a logic zero is represented by a low-to-high transition. The unit operating baud rate (in Mbaud) is equal to the input clock frequency (in MHZ) . All pins marked N/C must be left unconnected.

PIN DESCRIPTIONS

DAT	Data Input
CLK	Clock Input
RESB	Reset
TX	Signal Output
TXB	Inverted Signal Output
VCC	+5 Volts
GND	Ground

The all-CMOS 3D7501 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL Manchester Encoder. It is TTLand CMOS-compatible, capable of driving ten 74LS-type loads. It is offered in standard 8-pin and 14-pin auto-insertable DIPs and space saving surface mount 8-pin and 14pin SOICs.

Doc #96010

DATA DELAY DEVICES, INC.

5/19/97

3 Mt. Prospect Ave. Clifton, NJ 07013

3D7501

APPLICATION NOTES

The 3D7501 Manchester Encoder samples the data input at the rising edge of the input clock. The sampled data is used in conjunction with the clock rising and falling edges to generate the byphase level Manchester code.

INPUT SIGNAL CHARACTERISTICS

The 3D7501 Manchester Encoder inputs are

TTL compatible. The user should assure himself that the 1.5 volt TTL threshold is used when referring to all timing, especially to the input clock duty cycle.

CLOCK DUTY CYCLE ERRORS

The 3D7501 Manchester Encoder employs the timing of the clock rising and falling edges (duty cycle) to implement the required coding scheme. To reduce the difference between the output data high time and low time, it is essential that the deviation of the input clock duty cycle from 50/50 be minimized.

OUTPUT SIGNAL CHARACTERISTICS

The 3D7501 presents at its outputs the true and the complimented encoded data.

The High-to-Low time skew of the selected data output should be budgeted by the user, as it relates to his application, to satisfactorily estimate the distortion of the transmitted data stream.

Such estimate is very useful in determining the functionality and margins of the data link, if a 3D7502 Manchester Decoder is used to decode the received data.

POWER SUPPLY AND TEMPERATURE CONSIDERATIONS

CMOS integrated circuitry is strongly dependent on power supply and temperature. The monolithic 3D7501 Manchester encoder utilizes novel and innovative compensation circuitry to minimize timing variations induced by fluctuations in power supply and/or temperature.