DADD 3D7408S-5, 3D7408S-4, 3D7408S-3, 3D7408S-2, 3D7408S-1 Datasheet

3D7408

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7408)

data 3 ® delay

devices, inc.

FEATURES

∙All-silicon, low-power CMOS technology

∙TTL/CMOS compatible inputs and outputs

∙Vapor phase, IR and wave solderable

∙Auto-insertable (DIP pkg.)

∙Low ground bounce noise

∙Leadingand trailing-edge accuracy

∙Increment range: 0.25 through 5.0ns

∙Delay tolerance: 1% (See Table 1)

∙Temperature stability: ±3% typical (0C-70C)

∙Vdd stability: ±1% typical (4.75V-5.25V)

∙Minimum input pulse width: 10% of total delay

∙Programmable via 3-wire serial or 8-bit parallel interface

PACKAGES

IN		1	16		VDD
AE			15		OUT
		2
SO/P0		3	14		MD
P1		4	13		P7
P2		5	12		P6	IN		1	16	VDD
						AE		2	15	OUT
P3		6	11		SC	SO/P0		3	14	MD
						P1		4	13	P7
P4		7	10		P5	P2		5	12	P6
						P3		6	11	SC
GND		8	9		SI	P4		7	10	P5
						GND		8	9	SI
3D7408			DIP					3D7408S
3D7408G			Gull Wing						SOIC
		(300 Mil)						(300 Mil)

(For mechanical data, see Case Dimensions document)

FUNCTIONAL DESCRIPTION

The 3D7408 Programmable 8-Bit Silicon Delay Line product family consists of 8-bit, user-programmable CMOS silicon integrated circuits. Delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps ranging from 250ps to 5.0ns inclusively. Units have a typical inherent (zero step) delay of 12ns to 17ns (See Table 1). The input is reproduced at the output without inversion, shifted in time as per user selection. The 3D7408 is TTLand CMOScompatible, capable of driving ten 74LS-type loads, and features both risingand falling-edge accuracy.

PIN DESCRIPTIONS

IN	Signal Input
OUT	Signal Output
MD	Mode Select
AE	Address Enable
P0-P7	Parallel Data Input
SC	Serial Clock
SI	Serial Data Input
SO	Serial Data Output
VCC	+5 Volts
GND	Ground

The all-CMOS 3D7408 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

	PART	DELAYS AND TOLERANCES						INPUT RESTRICTIONS
	NUMBER	Step 0	Step 255			Delay	Max Operating	Absolute Max		Min Operating	Absolute Min
		Delay (ns)	Delay (ns)			Increment (ns)	Frequency	Oper Freq		P.W.	Oper P.W.
	3D7408-0.25	12 ± 2	75.75 ± 4.0			0.25 ± 0.15	6.25 MHz	90	MHz	80.0 ns	5.5 ns
	3D7408-0.5	12 ± 2	139.5 ± 4.0			0.50 ± 0.25	3.15 MHz	45	MHz	160.0 ns	11.0 ns
	3D7408-1	12 ± 2	267.0	± 5.0		1.00 ± 0.50	1.56 MHz	22	MHz	320.0 ns	22.0 ns
	3D7408-2	14 ± 2	522.0	± 6.0		2.00 ± 1.00	0.78 MHz	11	MHz	640.0 ns	44.0 ns
	3D7408-3	17 ± 2	782.0	± 8.0		3.00 ± 1.50	0.52 MHz	7.5	MHz	960.0 ns	66.0 ns
	3D7408-4	17 ± 2	1037	± 9.0		4.00 ± 2.00	0.39 MHz	5.5	MHz	1280.0 ns	88.0 ns
	3D7408-5	17 ± 2	1292 ± 10			5.00 ± 2.50	0.31 MHz	4.4 MHz		1600.0 ns	110.0 ns
	NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.									©1996 Data Delay Devices
	All delays referenced to input pin
	Doc #96003					DATA DELAY DEVICES, INC.					1

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3 Mt. Prospect Ave. Clifton, NJ 07013

3D7408

APPLICATION NOTES

The 8-bit programmable 3D7408 delay line architecture is comprised of a number of delay cells connected in series with their respective outputs multiplexed onto the Delay Out pin (OUT) by the user-selected programming data. Each delay cell produces at its output a replica of the signal present at its input, shifted in time.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay and increment accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a

Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.

The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7408 must be tested at the user operating frequency.

Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7408 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

SPECIAL HIGH ACCURACY

REQUIREMENTS

The Table 1 delay and increment accuracy specifications are aimed at meeting the requirements of the majority of the applications encountered to date. However, some systems may place tighter restrictions on one accuracy parameter in favor of others. For example, a channel delay equalizing system is concerned in minimizing delay variations among the various channels. Therefore, because the inter channel skew is a delay difference, the programmed delay tolerance may need to be considerably decreased, while the increment and its tolerance are of no consequence. The opposite is true for an under-sampled multi-channel data acquisition system.

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3D7408

APPLICATION NOTES (CONT’D)

The flexible 3D7408 architecture can be exploited to conform to these more demanding user-dictated accuracy constraints. However, to facilitate production and device identification, the part number will include a custom reference designator identifying the user requested accuracy specifications and operating conditions.

It is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

POWER SUPPLY AND TEMPERATURE CONSIDERATIONS

The delay of CMOS integrated circuits is strongly dependent on power supply and temperature. The monolithic 3D7408 programmable delay line utilizes novel and innovative compensation circuitry to minimize the delay variations induced by fluctuations in power supply and/or temperature.

The thermal coefficient is reduced to 600 PPM/C, which is equivalent to a variation, over the 0C-70 C operating range, of ±3% from the room-temperature delay settings. The power supply coefficient is reduced, over the 4.75V- 5.25V operating range, to ±1% of the delay settings at the nominal 5.0VDC power supply and/or ±2ns, whichever is greater.

It is essential that the power supply pin be adequately bypassed and filtered. In addition, the power bus should be of as low an impedance construction as possible. Power planes are preferred.

PROGRAMMED DELAY (ADDRESS) UPDATE

A delay line is a memory device. It stores information present at the input for a time equal to the delay setting before presenting it at the output with minimal distortion. The 3D7408 8-bit programmable delay line can be represented by 256 serially connected delay elements (individually addressed by the programming data), each capable of storing data for a time equal to the device increment (step time). The delay line memory property, in conjunction with the operational requirement of “instantaneously” connecting the delay element addressed by the programming data to the output, may inject spurious information onto the output data stream.

In order to ensure that spurious outputs do not occur, it is essential that the input signal be idle (held high or low) for a short duration prior to updating the programmed delay. This duration is given by the maximum programmable delay. Satisfying this requirement allows the delay line to “clear” itself of spurious edges. When the new address is loaded, the input signal can begin to switch (and the new delay will be valid) after a time given by tPDV or tEDV (see section below).

PROGRAMMED DELAY (ADDRESS)

INTERFACE

Figure 1 illustrates the main functional blocks of the 3D7408 delay program interface. Since the 3D7408 is a CMOS design, all unused input pins must be returned to well defined logic levels, VCC or Ground.

TRANSPARENT PARALLEL MODE (MD = 1, AE = 1)

The eight program pins P0 - P7 directly control the output delay. A change on one or more of the program

pins will be reflected on the output delay after a time tPDV, as shown in Figure 2. A register is required if the programming data is bused.

LATCHED PARALLEL MODE (MD = 1, AE PULSED)

The eight program pins P0 - P7 are loaded by the falling edge of the Enable pulse, as shown in Figure 3. After each change in delay value, a settling time tEDV is required before the input is accurately delayed.

SERIAL MODE (MD = 0)

While observing data setup (tDSC) and data hold (tDHC) requirements, timing data is loaded in MSB-to-LSB order by the rising edge of the clock (SC) while the enable (AE) is high, as shown in Figure 4. The falling edge of the enable (AE) activates the new delay value which is reflected at the output after a settling time tEDV. As data is shifted into the serial data input (SI), the previous contents of the 8-bit input register are shifted out of the serial output port pin (SO) in MSB-to-LSB order, thus allowing cascading of multiple devices by connecting the serial output pin (SO) of the preceding device to the serial data input

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