DADD 3D7303Z-500, 3D7303Z-50, 3D7303Z-400, 3D7303Z-40, 3D7303Z-300 Datasheet

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3D7303

 

 

 

 

 

 

MONOLITHIC TRIPLE

 

data

 

 

®

 

3

FIXED DELAY LINE

 

delay

 

(SERIES 3D7303)

 

devices, inc.

 

 

 

 

 

FEATURES

PACKAGES

 

 

All-silicon, low-power CMOS technology

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP pkg.)

Low ground bounce noise

Leadingand trailing-edge accuracy

Delay range: 10 through 500ns

Delay tolerance: 2% or 1.0ns

Temperature stability: ±3% typical (0C-70C)

Vdd stability: ±1% typical (4.75V-5.25V)

Minimum input pulse width: 20% of total delay

14-pin DIP available as drop-in replacement for hybrid delay lines

I1

 

1

 

8

 

 

VDD

I1

 

1

14

 

VDD

 

 

 

 

 

 

I2

 

 

 

 

7

 

 

O1

N/C

 

2

13

 

N/C

 

2

 

 

 

 

 

I3

 

3

 

6

 

 

O2

I2

 

3

12

 

O1

 

 

 

 

 

GND

 

4

 

5

 

 

O3

N/C

 

4

11

 

N/C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I3

 

5

10

 

O2

3D7303M

DIP

 

 

 

 

 

 

 

 

 

3D7303H

Gull-Wing

N/C

 

6

9

 

N/C

 

 

 

 

(300 Mil)

 

GND

 

7

8

 

O3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3D7303

 

DIP

 

 

I1

 

 

 

1

8

 

 

 

VDD

 

 

 

I2

 

 

2

7

 

 

 

O1

3D7303G

Gull-Wing

I3

 

 

3

6

 

 

 

O2

3D7303K

Unused pins

GND

 

 

4

5

 

 

 

O3

 

 

 

 

 

 

 

 

 

 

 

 

 

removed

3D7303Z

SOIC

 

 

 

 

 

(300 Mil)

 

 

 

 

(150 Mil)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FUNCTIONAL DESCRIPTION

PIN DESCRIPTIONS

The 3D7303 Triple Delay Line product family consists of fixed-delay

I1

Delay Line 1 Input

CMOS integrated circuits. Each package contains three matched,

I2

Delay Line 2 Input

independent delay lines. Delay values can range from 10ns through

I3

Delay Line 3 Input

500ns. The input is reproduced at the output without inversion,

O1

Delay Line 1 Output

shifted in time as per the user-specified dash number. The 3D7303

O2

Delay Line 2 Output

is TTLand CMOS-compatible, capable of driving ten 74LS-type

O3

Delay Line 3 Output

loads, and features both risingand falling-edge accuracy.

VCC

+5 Volts

 

GND

Ground

The all-CMOS 3D7303 integrated circuit has been designed as a

N/C

No Connection

reliable, economic alternative to hybrid TTL fixed delay lines. It is

 

 

offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

TABLE 1: PART NUMBER SPECIFICATIONS

 

 

 

PART NUMBER

 

DELAY

 

INPUT RESTRICTIONS

 

 

 

DIP-8

 

SOIC-8

DIP-14

DIP-14

PER LINE

Max Operating

Absolute Max

Min Operating

Absolute Min

 

3D7303M

 

3D7303Z

3D7303

3D7303K

(ns)

Frequency

Oper. Freq.

Pulse Width

Oper. P.W.

 

3D7303H

 

 

3D7303G

 

 

 

 

 

 

 

 

 

 

-10

 

-10

-10

-10

10

± 1.0

33.3 MHz

100.0

MHz

15.0 ns

5.0 ns

 

-15

 

-15

-15

-15

15

± 1.0

22.2 MHz

100.0

MHz

22.5 ns

5.0 ns

 

-20

 

-20

-20

-20

20

± 1.0

16.7 MHz

100.0

MHz

30.0 ns

5.0 ns

 

-25

 

-25

-25

-25

25

± 1.0

13.3 MHz

83.3

MHz

37.5 ns

6.0 ns

 

-30

 

-30

-30

-30

30

± 1.0

11.1 MHz

71.4

MHz

45.0 ns

7.0 ns

 

-40

 

-40

-40

-40

40

± 1.0

8.33 MHz

62.5

MHz

60.0 ns

8.0 ns

 

-50

 

-50

-50

-50

50

± 1.0

6.67 MHz

50.0

MHz

75.0 ns

10.0 ns

 

-100

 

-100

-100

-100

100

± 2.0

3.33 MHz

25.0

MHz

150.0 ns

20.0 ns

 

-200

 

-200

-200

-200

200

± 4.0

1.67 MHz

12.5

MHz

300.0 ns

40.0 ns

 

-300

 

-300

-300

-300

300

± 6.0

1.11 MHz

8.33

MHz

450.0 ns

60.0 ns

 

-400

 

-400

-400

-400

400

± 8.0

0.83 MHz

6.25

MHz

600.0 ns

80.0 ns

 

-500

 

-500

-500

-500

500 ± 10.0

0.67 MHz

5.00

MHz

750.0 ns

100.0 ns

 

NOTE:

Any delay between 10 and 500 ns not shown is also available.

 

 

©1996 Data Delay Devices

 

 

 

 

 

 

 

 

 

 

 

 

 

Doc #96001

 

DATA DELAY DEVICES, INC.

 

 

1

 

12/2/96

3 Mt. Prospect Ave. Clifton, NJ 07013

DADD 3D7303Z-500, 3D7303Z-50, 3D7303Z-400, 3D7303Z-40, 3D7303Z-300 Datasheet

3D7303

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7303 triple delay line architecture is shown in Figure 1. The individual delay lines are composed of a number of delay cells connected in series. Each delay line produces at its output a replica of the signal present at its input, shifted in time. The delay lines are matched and share the same compensation signals, which minimizes line-to-line delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7303 must be tested at the user operating frequency.

Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.

The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7303 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a

VDD

O1

O2

O3

Temp & VDD

Delay

Delay

Delay

Compensation

Line

Line

Line

GND

I1

I2

I3

Figure 1: 3D7303 Functional Diagram

Doc #96001

DATA DELAY DEVICES, INC.

2

12/2/96

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

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