MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7205)
FEATURES
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All-silicon, low-power CMOS |
O2 |
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2 |
7 |
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O1 |
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IN |
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1 |
8 |
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VDD |
∙ |
technology |
O4 |
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3 |
6 |
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O3 |
TTL/CMOS compatible |
GND |
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4 |
5 |
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O5 |
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inputs and outputs |
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3D7205Z |
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∙ Vapor phase, IR and wave |
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SOIC |
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solderable |
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(150 Mil) |
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∙Auto-insertable (DIP pkg.)
∙Low ground bounce noise
∙Leadingand trailing-edge accuracy
∙Delay range: 8 through 500ns
∙Delay tolerance: 5% or 2ns
∙Temperature stability: ±3% typical (0C-70C)
∙Vdd stability: ±2% typical (4.75V-5.25V)
∙Minimum input pulse width: 20% of total delay
∙14-pin DIP and 16-pin SOIC available as drop-in replacements for hybrid delay lines
3D7205
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data |
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delay |
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devices, inc. |
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PACKAGES |
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IN |
1 |
8 |
VDD |
IN |
1 |
14 |
VDD |
O2 |
2 |
7 |
O1 |
N/C |
2 |
13 |
N/C |
O4 |
3 |
6 |
O3 |
N/C |
3 |
12 |
O1 |
GND |
4 |
5 |
O5 |
O2 |
4 |
11 |
N/C |
3D7205M |
DIP |
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N/C |
5 |
10 |
O3 |
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3D7205H |
Gull-Wing |
O4 |
6 |
9 |
N/C |
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(300 Mil) |
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GND |
7 |
8 |
O5 |
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IN |
1 |
16 |
VDD |
3D7205 |
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DIP |
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N/C |
2 |
15 |
N/C |
3D7205G |
Gull-Wing |
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N/C |
3 |
14 |
N/C |
3D7205K |
Unused pins |
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O2 |
4 |
13 |
O1 |
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N/C |
5 |
12 |
N/C |
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removed |
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O4 |
6 |
11 |
O3 |
(300 Mil) |
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N/C |
7 |
10 |
N/C |
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GND |
8 |
9 |
O5 |
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3D7205S SOIC
(300 Mil)
FUNCTIONAL DESCRIPTION |
PIN DESCRIPTIONS |
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The 3D7205 5-Tap Delay Line product family consists of fixed-delay |
IN |
Delay Line Input |
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CMOS integrated circuits. Each package contains a single delay line, |
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O1 |
Tap 1 Output (20%) |
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tapped and buffered at 5 points spaced uniformly in time. Tap-to-tap |
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O2 |
Tap 2 Output (40%) |
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(incremental) delay values can range from 8.0ns through 100ns. The |
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O3 |
Tap 3 Output (60%) |
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input is reproduced at the outputs without inversion, shifted in time as per |
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O4 |
Tap 4 Output (80%) |
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the user-specified dash number. The 3D7205 is TTLand CMOS- |
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O5 |
Tap 5 Output (100%) |
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compatible, capable of driving ten 74LS-type loads, and features both |
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VCC |
+5 Volts |
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risingand falling-edge accuracy. |
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GND |
Ground |
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The all-CMOS 3D7205 integrated circuit has been designed as a reliable, |
N/C |
No Connection |
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economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
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PART NUMBER |
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TOLERANCES |
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INPUT RESTRICTIONS |
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DIP-8 |
SOIC-8 |
DIP-14 |
SOIC-16 |
TOTAL |
TAP-TAP |
Max |
Absolute |
Min |
Absolute |
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3D7205M |
3D7205Z |
3D7205 |
3D7205S |
DELAY (ns) |
DELAY |
Operating |
Max |
Operating |
Min |
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3D7205H |
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3D7205G |
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(ns) |
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Frequency |
Oper. Freq. |
Pulse Width |
Oper. P.W. |
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3D7205K |
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-8 |
-8 |
-8 |
-8 |
40.0 |
± 2.0 |
8.0 |
± |
1.5 |
9.52 MHz |
71.4 MHz |
52.5 ns |
7.0 ns |
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-10 |
-10 |
-10 |
-10 |
50.0 |
± 2.5 |
10.0 |
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2.0 |
6.67 MHz |
50.0 MHz |
75.0 ns |
10.0 ns |
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-15 |
-15 |
-15 |
-15 |
75.0 |
± 3.8 |
15.0 |
± |
2.3 |
4.44 MHz |
33.3 MHz |
113 ns |
15.0 ns |
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-20 |
-20 |
-20 |
-20 |
100 |
± 5.0 |
20.0 |
± |
2.5 |
3.33 MHz |
25.0 MHz |
150 ns |
20.0 ns |
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-25 |
-25 |
-25 |
-25 |
125 |
± 6.3 |
25.0 |
± |
2.5 |
2.66 MHz |
20.0 MHz |
188 ns |
25.0 ns |
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-30 |
-30 |
-30 |
-30 |
150 |
± 7.5 |
30.0 |
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3.0 |
2.22 MHz |
16.7 MHz |
225 ns |
30.0 ns |
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-50 |
-50 |
-50 |
-50 |
250 ± 12.5 |
50.0 |
± |
5.0 |
1.33 MHz |
10.0 MHz |
375 ns |
50.0 ns |
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-75 |
-75 |
-75 |
-75 |
375 ± 18.8 |
75.0 |
± |
7.5 |
0.89 MHz |
6.67 MHz |
563 ns |
75.0 ns |
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-100 |
-100 |
-100 |
-100 |
500 ± 25.0 |
100 ± 10.0 |
0.67 MHz |
5.00 MHz |
750 ns |
100.0 ns |
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NOTE: |
Any dash number between 8 and 100 not shown is also available. |
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©1996 Data Delay Devices |
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Doc #96007 |
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DATA DELAY DEVICES, INC. |
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1 |
12/2/96 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
3D7205
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7205 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or PulseWidth (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.
To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7205 must be tested at the user operating frequency.
Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest PulseWidth of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.
The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.
The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.
To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7205 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a
IN |
O1 |
O2 |
O3 |
O4 |
O5 |
20% |
20% |
20% |
20% |
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20% |
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Temp & VDD |
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Compensation |
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VDD |
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GND |
Figure 1: 3D7205 Functional Diagram
Doc #96007 |
DATA DELAY DEVICES, INC. |
2 |
12/2/96 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |