DADD 3D7110S-8, 3D7110S-5, 3D7110S-4, 3D7110S-2.5, 3D7110S-2 Datasheet

...
0 (0)

3D7110

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7110)

data 3 ® delay

devices, inc.

FEATURES

 

 

 

PACKAGES

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All-silicon, low-power CMOS technology

IN

 

1

14

 

 

VDD

IN

 

 

1

14

VDD

 

 

 

N/C

 

 

2

13

O1

 

TTL/CMOS compatible inputs and outputs

N/C

 

2

13

 

 

O1

O4

 

 

4

11

O5

 

Vapor phase, IR and wave solderable

 

 

 

 

 

 

 

O2

 

 

3

12

O3

 

O2

 

3

12

 

 

O3

O6

 

 

5

10

O7

 

 

 

 

 

Auto-insertable (DIP pkg.)

 

 

 

 

 

 

 

O8

 

 

6

9

O9

 

 

 

 

 

 

 

 

GND

 

 

7

8

O10

 

Low ground bounce noise

O4

 

4

11

 

 

O5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Leadingand trailing-edge accuracy

O6

 

5

10

 

 

O7

 

3D7110D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SOIC

 

 

 

Delay range: .75 through 80ns

O8

 

6

9

 

 

O9

 

(150 Mil)

 

 

 

 

 

 

 

 

Delay tolerance: 5% or 1ns

GND

 

7

8

 

 

O10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Temperature stability: ±3% typical (0C-70C)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3D7110

DIP

 

N/C

 

2

 

 

 

15

 

N/C

Vdd stability: ±1% typical (4.75V-5.25V)

 

 

 

 

 

 

 

IN

 

1

 

 

 

16

 

VDD

3D7110G

Gull-Wing

N/C

 

3

 

 

 

14

 

O1

Minimum input pulse width: 15% of total delay

 

 

(300 Mil)

 

O2

 

4

 

 

 

13

 

O3

 

 

 

O4

 

5

 

 

 

12

 

O5

14-pin Gull-Wing and 16-pin SOIC available as

 

 

 

 

 

 

 

O8

 

7

 

 

 

10

 

O9

 

 

 

 

 

 

 

 

 

O6

 

6

 

 

 

11

 

O7

 

drop-in replacements for hybrid delay lines

 

 

 

 

 

 

 

GND

 

8

 

 

 

9

 

O10

3D7110S SOIC

(300 Mil)

(For mechanical data, see Case Dimensions document)

FUNCTIONAL DESCRIPTION

The 3D7110 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 8.0ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7110 is TTLand CMOScompatible, capable of driving ten 74LS-type loads, and features both risingand falling-edge accuracy.

The all-CMOS 3D7110 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14and 16-pin SOIC packages.

PIN DESCRIPTIONS

IN

Delay Line Input

O1

Tap 1 Output (10%)

O2

Tap 2 Output (20%)

O3

Tap 3 Output (30%)

O4

Tap 4 Output (40%)

O5

Tap 5 Output (50%)

O6

Tap 6 Output (60%)

O7

Tap 7 Output (70%)

O8

Tap 8 Output (80%)

O9

Tap 9 Output (90%)

O10

Tap 10 Output (100%)

VCC

+5 Volts

GND

Ground

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

 

 

TOLERANCES

 

INPUT RESTRICTIONS

 

DIP-14

SOIC-14

 

SOIC-16

TOTAL

TAP-TAP

Max

Absolute

Min

Absolute

3D7110

3D7110D

 

3D7110S

DELAY

DELAY

Operating

Max

 

Operating

Min

3D7110G

 

 

 

(ns)

(ns)

Frequency

Oper. Freq.

Pulse Width

Oper. P.W.

-.75

-.75

 

-.75

6.75

± 1.0*

0.75

± 0.4

28.4 MHz

166.7

MHz

17.6 ns

3.00 ns

-1

-1

 

-1

9.0

± 1.0*

1.0

± 0.5

23.8 MHz

166.7

MHz

21.0 ns

3.00 ns

-1.5

-1.5

 

-1.5

13.5

± 1.0*

1.5

± 0.7

18.0 MHz

166.7

MHz

27.8 ns

3.00 ns

-2

-2

 

-2

18.0

± 1.0*

2.0

± 0.8

14.5 MHz

166.7

MHz

34.5 ns

3.00 ns

-2.5

-2.5

 

-2.5

22.5

± 1.1*

2.5

± 1.0

18.2 MHz

125.0

MHz

27.5 ns

4.00 ns

-4

-4

 

-4

36.0

± 1.8*

4.0

± 1.3

8.33 MHz

133.3

MHz

60.0 ns

6.00 ns

-5

-5

 

-5

50.0 ± 2.5

5.0

± 1.5

6.67 MHz

66.7

MHz

75.0 ns

7.50 ns

-8

-8

 

-8

80.0 ± 4.0

8.0

± 1.5

4.17 MHz

41.7

MHz

120.0 ns

12.0 ns

* Total delay referenced to Tap1 output; Input-to-Tap1 = 5.0ns ± 1.0ns

©1996 Data Delay Devices

NOTE: Any dash number between .75 and 8 not shown is also available.

 

 

 

Doc #96005

DATA DELAY DEVICES, INC.

1

12/2/96

3 Mt. Prospect Ave. Clifton, NJ 07013

DADD 3D7110S-8, 3D7110S-5, 3D7110S-4, 3D7110S-2.5, 3D7110S-2 Datasheet

3D7110

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7110 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to- tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7110 must be tested at the user operating frequency.

Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.

The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7110 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a

IN

O1

O2

O3

O4

O5

O6

O7

O8

O9

O10

10%

10%

10%

10%

10%

10%

10%

10%

10%

 

10%

 

 

 

 

Temp & VDD

 

 

 

 

 

 

 

 

 

Compensation

 

 

 

 

 

VDD

 

 

 

 

 

 

 

 

 

GND

Figure 1: 3D7110 Functional Diagram

Doc #96005

DATA DELAY DEVICES, INC.

2

12/2/96

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

Loading...
+ 2 hidden pages