DADD 3D7010S-90, 3D7010S-80, 3D7010S-500, 3D7010S-400, 3D7010S-300 Datasheet

...
0 (0)

3D7010

MONOLITHIC 10-TAP FIXED DELAY LINE (SERIES 3D7010)

data 3 ® delay

devices, inc.

FEATURES

All-silicon, low-power CMOS technology*

TTL/CMOS compatible inputs and outputs

Vapor phase, IR and wave solderable

Auto-insertable (DIP package)

Low ground bounce noise

Leadingand trailing-edge accuracy

Delay range: 8 through 500ns

Delay tolerance: 5% or 2ns

Temperature stability: ±3% typical (0C-70C)

Vdd stability: ±2% typical (4.75V-5.25V)

Minimum input pulse width: 20% of total delay

PACKAGES

IN

 

1

14

 

VDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N/C

 

 

13

 

O1

 

 

 

 

 

 

2

 

 

 

 

 

 

O2

 

3

12

 

O3

 

 

 

 

 

 

 

 

 

 

 

 

O4

 

4

11

 

O5

IN

 

1

16

VDD

 

 

N/C

 

2

15

N/C

O6

 

5

10

 

O7

N/C

 

3

14

O1

 

 

O2

 

4

13

O3

O8

 

6

9

 

O9

O4

 

5

12

O5

 

 

O6

 

6

11

O7

GND

 

7

8

 

O10

O8

 

7

10

O9

 

 

GND

 

8

9

O10

 

 

 

 

 

 

3D7010

DIP

3D7010S

3D7010G

Gull-Wing

SOIC

(300 Mil)

(300 Mil)

(For mechanical data, see Case Dimensions document)

FUNCTIONAL DESCRIPTION

The 3D7010 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 8ns through 50ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D7010 is TTLand CMOScompatible, capable of driving ten 74LS-type loads, and features both risingand falling-edge accuracy.

The all-CMOS 3D7010 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

PIN DESCRIPTIONS

IN

Delay Line Input

O1

Tap 1 Output (10%)

O2

Tap 2 Output (20%)

O3

Tap 3 Output (30%)

O4

Tap 4 Output (40%)

O5

Tap 5 Output (50%)

O6

Tap 6 Output (60%)

O7

Tap 7 Output (70%)

O8

Tap 8 Output (80%)

O9

Tap 9 Output (90%)

O10

Tap 10 Output (100%)

VCC

+5 Volts

GND

Ground

TABLE 1: PART NUMBER SPECIFICATIONS

PART NUMBER

 

TOLERANCES

 

 

INPUT RESTRICTIONS

 

DIP-14

SOIC-16

TOTAL

TAP-TO-TAP

Max Operating

Absolute Max

Min Operating

Absolute Min

3D7010

3D7010S

DELAY

DELAY

Frequency

Oper. Freq.

Pulse Width

Oper. P.W.

3D7010G

 

(ns)

(ns)

 

 

 

 

 

-80

-80

80

± 4.0

8.0

± 1.5

4.17 MHz

31.2 MHz

120.0 ns

16.0 ns

-90

-90

90

± 4.5

9.0

± 1.7

3.70 MHz

27.8 MHz

135.0 ns

18.0 ns

-100

-100

100

± 5.0

10.0

± 2.0

3.33 MHz

25.0 MHz

150.0 ns

20.0 ns

-150

-150

150

± 7.5

15.0

± 2.0

2.22 MHz

16.7 MHz

225.0 ns

30.0 ns

-200

-200

200 ± 10.0

20.0

± 2.5

1.67 MHz

12.5 MHz

300.0 ns

40.0 ns

-250

-250

250 ± 12.5

25.0

± 2.5

1.33 MHz

10.0 MHz

375.0 ns

50.0 ns

-300

-300

300 ± 15.0

30.0

± 3.0

1.11 MHz

8.33 MHz

450.0 ns

60.0 ns

-400

-400

400 ± 20.0

40.0

± 4.0

0.83 MHz

6.25 MHz

600.0 ns

80.0 ns

-500

-500

500 ± 25.0

50.0

± 5.0

0.67 MHz

5.00 MHz

750.0 ns

100.0 ns

NOTE: Any dash number between 80 and 500 not shown is also available.

©1996 Data Delay Devices

*PATENTED

 

 

 

 

 

 

 

 

Doc #96004

DATA DELAY DEVICES, INC.

1

12/2/96

3 Mt. Prospect Ave. Clifton, NJ 07013

DADD 3D7010S-90, 3D7010S-80, 3D7010S-500, 3D7010S-400, 3D7010S-300 Datasheet

3D7010

APPLICATION NOTES

OPERATIONAL DESCRIPTION

The 3D7010 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to- tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS

The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D7010 must be tested at the user operating frequency.

Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all.

Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH

The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.

OPERATING FREQUENCY

The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.

The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D7010 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a

IN

O1

O2

O3

O4

O5

O6

O7

O8

O9

O10

10%

10%

10%

10%

10%

10%

10%

10%

10%

 

10%

 

 

 

 

Temp & VDD

 

 

 

 

 

 

 

 

 

Compensation

 

 

 

 

 

VDD

 

 

 

 

 

 

 

 

 

GND

Figure 1: 3D7010 Functional Diagram

Doc #96004

DATA DELAY DEVICES, INC.

2

12/2/96

Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com

Loading...
+ 2 hidden pages