MONOLITHIC 5-TAP 3.3V FIXED DELAY LINE (SERIES 3D3215)
FEATURES
∙All-silicon, low-power 3.3V CMOS technology
∙Vapor phase, IR and wave solderable
∙Auto-insertable (DIP pkg.)
∙Low ground bounce noise
∙Leadingand trailing-edge accuracy
∙Delay range: 1.5ns through 300ns
∙Total delay tolerance: 2% or 0.5ns (3.3V, 25C)
∙Temperature stability: ±1% typical (0C-70C)
∙Vdd stability: ±1% typical (3.0V-3.6V)
∙Static Idd: 1.3ma typical
∙Minimum input pulse width: 25% of total delay
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3D3215 |
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data |
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® |
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3 |
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delay |
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devices, inc. |
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PACKAGES |
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IN |
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1 |
8 |
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VDD |
IN |
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1 |
8 |
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VDD |
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O2 |
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2 |
7 |
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O1 |
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O4 |
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3 |
6 |
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O3 |
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O2 |
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2 |
7 |
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O1 |
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GND |
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4 |
5 |
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O5 |
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O4 |
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O3 |
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3D3215Z-xx |
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3 |
6 |
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SOIC (150 Mil) GND |
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4 |
5 |
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O5 |
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3D3215M-xx DIP (300 Mil)
For mechanical dimensions, click here. For package marking details, click here.
FUNCTIONAL DESCRIPTION
The 3D3215 5-Tap Delay Line product family consists of fixed-delay 3.3V CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 5 points spaced uniformly in time. Tap-to- tap (incremental) delay values can range from 1.5ns through 60ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number. The 3D3215 is 3.3V CMOScompatible and features both risingand falling-edge accuracy.
The all-CMOS 3D3215 integrated circuit has been designed as a reliable, economic alternative to hybrid fixed delay lines. It is offered in a
standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
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DASH # |
DELAY SPECIFICATIONS |
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INPUT RESTRICTIONS |
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3D3215Z-xx |
TOTAL |
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TAP-TAP |
RECOMMENDED |
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ABSOLUTE |
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3D3215M-xx |
DELAY (ns) |
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DELAY (ns) |
Max Freq |
Min P.W. |
Max Freq |
Min P.W. |
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-1.5 |
6.0 ± 0.5* |
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1.5 ± 0.7 |
23.8 MHz |
21.0 ns |
83.3 |
MHz |
6.00 ns |
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-2 |
8.0 ± 0.5* |
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2.0 ± 0.8 |
20.8 MHz |
24.0 ns |
83.3 |
MHz |
6.00 ns |
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-2.5 |
10.0 |
± 0.5* |
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2.5 ± 1.0 |
18.5 MHz |
27.0 ns |
66.7 |
MHz |
7.50 ns |
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-3 |
12.0 |
± 0.5* |
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3.0 ± 1.3 |
16.7 MHz |
30.0 ns |
55.6 |
MHz |
9.00 ns |
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-4 |
16.0 |
± 0.5* |
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4.0 ± 1.3 |
13.9 MHz |
36.0 ns |
50.0 |
MHz |
10.00 ns |
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-5 |
20.0 |
± 0.5* |
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5.0 ± 1.4 |
11.9 MHz |
42.0 ns |
40.0 |
MHz |
12.50 ns |
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-6 |
24.0 |
± 0.5* |
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6.0 ± 1.4 |
10.4 MHz |
48.0 ns |
55.6 |
MHz |
9.00 ns |
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-8 |
40.0 |
± 0.8 |
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8.0 ± 1.4 |
8.33 MHz |
60.0 ns |
41.7 |
MHz |
12.00 ns |
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-10 |
50.0 |
± 1.0 |
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10.0 ± 1.5 |
6.67 MHz |
75.0 ns |
40.0 |
MHz |
12.50 ns |
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-12 |
60.0 |
± 1.2 |
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12.0 ± 1.5 |
5.56 MHz |
90.0 ns |
33.3 |
MHz |
15.00 ns |
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-15 |
75.0 |
± 1.5 |
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15.0 ± 1.5 |
4.42 MHz |
113 ns |
26.7 |
MHz |
18.75 ns |
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-20 |
100 |
± 2.0 |
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20.0 ± 2.0 |
3.33 MHz |
150 ns |
20.0 |
MHz |
25.00 ns |
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-25 |
125 |
± 2.5 |
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25.0 ± 2.5 |
2.66 MHz |
188 ns |
16.0 |
MHz |
31.25 ns |
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-30 |
150 |
± 3.0 |
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30.0 ± 3.0 |
2.22 MHz |
225 ns |
13.3 |
MHz |
37.50 ns |
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-40 |
200 |
± 4.0 |
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40.0 ± 4.0 |
1.67 MHz |
300 ns |
10.0 |
MHz |
50.00 ns |
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-50 |
250 |
± 5.0 |
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50.0 ± 5.0 |
1.33 MHz |
375 ns |
8.0 |
MHz |
62.50 ns |
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-60 |
300 |
± 6.0 |
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60.0 ± 6.0 |
1.11 MHz |
450 ns |
6.7 |
MHz |
75.00 ns |
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* Total delay referenced to Tap1 output; |
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Input-to-Tap1 = 7.5ns ± 1.5ns |
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©2001 Data Delay Devices |
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NOTE: Any dash number between 1.5 and 60 not shown is also available as standard |
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Doc #01014 |
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DATA DELAY DEVICES, INC. |
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1 |
12/3/01 |
3 Mt. Prospect Ave. Clifton, NJ 07013 |
3D3215
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D3215 five-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or PulseWidth (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Recommended Maximum and an Absolute Maximum operating input frequency and a Recommended Minimum and an Absolute Minimum operating pulse width have been specified.
delay accuracy is guaranteed. To guarantee the Table 1 delay accuracy for input frequencies higher than the Recommended Maximum Frequency, the 3D3215 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest PulseWidth of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion.
OPERATING FREQUENCY
The Absolute Maximum Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion.
The Recommended Maximum Frequency specification determines the highest frequency of the delay line input signal for which the output
The Recommended Minimum Pulse Width
(high or low) specification determines the smallest PulseWidth of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.
To guarantee the Table 1 delay accuracy for input pulse width smaller than the Recommended Minimum PulseWidth, the 3D3215 must be tested at the user operating pulse width. Therefore, to facilitate production and device
IN |
O1 |
O2 |
O3 |
O4 |
O5 |
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25% |
25% |
25% |
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25% |
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Temp & VDD |
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Compensation |
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IN |
O1 |
O2 |
O3 |
O4 |
O5 |
20% |
20% |
20% |
20% |
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20% |
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Temp & VDD |
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Compensation |
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Dash numbers < 8 |
Dash numbers >= 8 |
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VDD |
GND |
VDD |
GND |
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Figure 1: 3D3215 Functional Diagram |
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Doc #01014 |
DATA DELAY DEVICES, INC. |
2 |
12/3/01 |
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com |