Cypress Semiconductor GVT71512D18TA-6.7, GVT71512D18TA-6, GVT71512D18TA-5, GVT71512D18TA-4.4, GVT71512D18T-6.7 Datasheet

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256K x 36/512K x 18 Pipelined SRAM
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
May 9, 2001
1CY7C1329
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
•Fast OE
access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for depth expansion (one cycle chip deselect to eliminate bus contention)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to V
SS
at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write contr ol
• Multiple chip enables for depth expansion: three chip enables f or T A package ver sion and two chip enables for B and T packa ge ver s ions
• Address pipeline capability
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se­quence)
• Automatic po wer-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 11 9-bump, 14-mm x 22-mm PBGA (Ball Grid Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs high-speed, low-power CMOS designs using advanced tri­ple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors.
The CY7C1360A/GVT71256D36 and CY7C1362A/ GVT71512D18 SRAMs in tegrate 262 ,144x36 and 524,28 8x18 SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for inter nal burst operation. All synchro­nous inputs are gated by registers controlled by a posi­tive-edge-triggered Clock Input (CLK). The synchronous in­puts include all addresses, all data inputs, address-pipelining Chip Enable (CE
), depth-expansion Chip Enables (CE2 and CE2), burst control inpu ts (ADSC, ADSP, and ADV), Write En­ables (BWa
, BWb, BWc, BWd , and BWE), and global write
(GW
). However, the CE2 chip enable input i s only available for
the TA package version. Asynchronous inputs include the Output Enable (OE
) and burst mode cont rol (MODE). Th e data outp uts (Q), enab led b y OE
, are also asynchronous.
Addresses and chip enables are registered with either Ad­dress Status Processor (ADSP
) or Address Status Controller
(ADSC
) input pins. Subsequen t burst addresses can be inter-
nally generated as co ntrolled b y the Burst Advanc e Pin (AD V). Address, data in puts, an d write contro ls are registere d on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BW b, BWc, and BWd can be active only with BWE
being LOW. GW being LOW causes all bytes to be written. The x18 v ersion on ly has 18 data inpu ts/outputs (DQa and DQb) along with BW a
and BWb (no BWc, BWd, DQc , and
DQd). For the B a nd T pac kage v ers ions, four pins are used to imple-
ment JTAG test capabilitie s: Test Mode Select (TM S), Test Da­ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mo de of oper ation . The TA pac kage v ersio n does not offer the JTAG capability.
The CY7C1360A/GVT71256D36 and CY7C1362A/ GVT71512D18 operate from a +3.3V power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
7C1360A-225 71256D36-4.4 7C1362A-225 71512D18-4.4
7C1360A-200
71256D36-5
7C1362A-200
71512D18-5
7C1360A-166
71256D36-6
7C1362A-166
71512D18-6
7C1360A-150 71256D36-6.7 7C1362A-150 71512D18-6.7
Maximum Access Time (ns) 2.5 3.0 3.5 3.5 Maximum Operating Current (mA) Commercial 570 510 425 380 Maximum CMOS Standby Curren t (mA) 10 10 10 10
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
2
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
2. CE
2
is for TA version only.
DQ
DQ
BWb#
BWE#
BWa#
GW#
BYTE b WRITE
BYTE a
WRITE
OUTPUT
REGISTER
OE#
byte b write
ADSP#
ADSC#
Address Register
Binary
Counter
& Logic
CLR
A
A1-A0
ADV#
MODE
512K x 9 x 2
SRAM Array
Output Buffers
Input
Register
byte a write
DQa,DQb
DQ DQ
DQ
ENABLE
Power Down LogicZZ
17
CE#
CE2
CE2#
DQ
DQ
BWc#
BWE#
BWd#
BYTE c WRITE
BYTE d WRITE
OUTPUT
REGISTER
OE#
byte c write
ADSP#
ADSC#
Address Register
Binary
Counter
& Logic
CLR
A
A1-A0
ADV#
MODE
256K x 9 x 4
SRAM Array
Output Buffers
Input
Register
byte d write
DQa,DQb DQc,DQd
DQ
DQ
DQ
BWa#
BWb#
GW#
BYTE a WRITE
BYTE b WRITE
CLK
byte b write
byte a write
DQ
DQ
ENABLE
Power Down LogicZZ
16
CE#
CE2
CE2#
Functional Block Diagram—256K x 36
[1]
Functional Block Diagram—512K x 18
[1]
[2]
[2]
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
3
Pin Configurations
AAA
A
A1
A0
TMS
TDI
V
SS
V
CC
TDO
TCK
AAAAAAA
DQb DQb DQb V
CCQ
V
SS
DQb DQb DQb DQb V
SS
V
CCQ
DQb DQb V
SS
NC V
CC
ZZ DQa DQa V
CCQ
V
SS
DQa DQa DQa DQa V
SS
V
CCQ
DQa DQa DQa
DQc DQc DQc
V
CCQ
V
SS
DQc DQc DQc DQc
V
SS
V
CCQ
DQc DQc
V
CC
NC
V
SS
DQd DQd
V
CCQ
V
SS
DQd DQd DQd DQd
V
SS
V
CCQ
DQd DQd DQd
A
A
CE
CE
2
BWd
BWc
BWb
BWa
A
VCCV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31323334353637383940414243444546474849
50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100999897969594939291908988878685848382
81
MODE
CY7C1360A/GVT71256D36
(256K X 36)
NC
A NC NC V
CCQ
V
SS
NC DPa DQa DQa V
SS
V
CCQ
DQa DQa V
SS
NC V
CC
ZZ DQa DQa V
CCQ
V
SS
DQa DQa NC NC V
SS
V
DDQ
NC NC NC
NC NC NC
V
CCQ
V
SS
NC
NC DQb DQb
V
SS
V
CCQ
DQb DQb
V
CC
NC
V
SS
DQb DQb
V
CCQ
V
SS
DQb DQb DQb
NC
V
SS
V
CCQ
NC
NC
NC
AACE
CE2NCNCBWb
BWaAVCCV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31323334353637383940414243444546474849
50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100999897969594939291908988878685848382
81
CY7C1362A/GVT71512D18
(512K x 18)
NC
100-Pin TQFP
Top View
AAA
A
A1
A0
NC
NC
V
SS
V
CC
NC
AAAAAAA
A
DQb DQb DQb V
CCQ
V
SS
DQb DQb DQb DQb V
SS
V
CCQ
DQb DQb V
SS
NC V
CC
ZZ DQa DQa V
CCQ
V
SS
DQa DQa DQa DQa V
SS
V
CCQ
DQa DQa DQa
DQc DQc DQc
V
CCQ
V
SS
DQc DQc DQc DQc
V
SS
V
CCQ
DQc DQc
V
CC
NC
V
SS
DQd DQd
V
CCQ
V
SS
DQd DQd DQd DQd
V
SS
V
CCQ
DQd DQd DQd
A
A
CE
CE
2
BWd
BWc
BWb
BWa
CE2VCCV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31323334353637383940414243444546474849
50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100999897969594939291908988878685848382
81
MODE
CY7C1360A/GVT71256D36
(256K X 36)
NC
A NC NC V
CCQ
V
SS
NC DQa DQa DQa V
SS
V
CCQ
DQa DQa V
SS
NC V
CC
ZZ DQa DQa V
CCQ
V
SS
DQa DQa NC NC V
SS
V
CCQ
NC NC NC
NC
NC
NC
V
CCQ
V
SS
NC
NC DQb DQb
V
SS
V
CCQ
DQb DQb
V
CC
NC
V
SS
DQb DQb
V
CCQ
V
SS
DQb DQb DQb
NC
V
SS
V
CCQ
NC
NC
NC
AACE
CE2NCNCBWb
BWa
CE2VCCV
SS
CLKGWBWEOEADSC
ADSP
ADV
A
A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31323334353637383940414243444546474849
50
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100999897969594939291908988878685848382
81
CY7C1362A/GVT71512D18
(512K x 18)
NC
TA Package Version
TA Package Version
T Package Version
T Package Version
AAA
A
A1
A0
TMS
TDI
V
SS
V
CC
TDO
TCK
AAAAAAA
MODE
AAA
A
A1
A0
NC
NC
V
SS
V
CC
NC
AAAAAAA
A
MODE
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
4
Pin Configurations
(continued)
119-Ball BGA
1234567
A V
CCQ
A A ADSP AAV
CCQ
B NC CE
2
AADSCAANC
C NC A A V
CC
AANC
D DQc DQc V
SS
NC V
SS
DQb DQb
E DQc DQc V
SS
CE V
SS
DQb DQb
F V
CCQ
DQc V
SS
OE V
SS
DQb V
CCQ
G DQc DQc BWc
ADV BWb DQb DQb
H DQc DQc V
SS
GW V
SS
DQb DQb
J V
CCQ
V
CC
NC V
CC
NC V
CC
V
CCQ
K DQd DQd V
SS
CLK V
SS
DQa DQa
L DQd DQd BWd
NC BWa DQa DQa
M V
CCQ
DQd V
SS
BWE V
SS
DQa V
CCQ
N DQd DQd V
SS
A1 V
SS
DQa DQa
P DQd DQd V
SS
A0 V
SS
DQa DQa
R NC A MODE V
CC
NC A NC
T NC NC A A A NC ZZ
U V
CCQ
TMS TDI TCK TDO NC V
CCQ
Top View
1234567
A V
CCQ
A A ADSP AAV
CCQ
B NC CE
2
AADSCACE2NC
C NC A A V
CC
AANC
D DQb NC V
SS
NC V
SS
DQa NC
E NC DQb V
SS
CE V
SS
NC DQa
F V
CCQ
NC V
SS
OE V
SS
DQa V
CCQ
G NC DQb BWb
ADV V
SS
NC DQa
H DQb NC V
SS
GW V
SS
DQa NC
J V
CCQ
V
CC
NC V
CC
NC V
CC
V
CCQ
K NC DQb V
SS
CLK V
SS
NC DQa
L DQb NC V
SS
NC BWa DQa NC
M V
CCQ
DQb V
SS
BWE V
SS
NC V
CCQ
N DQb NC V
SS
A1 V
SS
DQa NC
P NC DQb V
SS
A0 V
SS
NC DQa
R NC A MODE V
CC
NC A NC
T NC A A NC A A ZZ
U V
CCQ
TMS TDI TCK TDO NC V
CCQ
256Kx36
512Kx18
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
5
256K X 36 Pin Descriptions
X36 PBGA Pins X36 QFP Pins Name Type Description
4P
4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 3T, 4T, 5T
37 36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47, 48,
49, 50
92 (T Version)
43 (TA Version)
A0 A1
A
Input-
Synchronous
Addresses: These inpu ts a re regis tered a nd m ust me et the set-up and hold times arou nd the rising edge of CLK. The burst counter generates internal addresses associ­ated with A0 and A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93 94 95 96
BWa BWb BWc BWd
Input-
Synchronous
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BWa
controls DQa. BWb con­trols DQb. BWc c ontrols D Qc. BW d controls DQd. Data I/O are high impedanc e if either of these in puts are LOW , conditioned by BWE
being LOW.
4M 87 BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK.
4H 88 GW
Input-
Synchronous
Global Write: This active LOW input allows a full 36-bit WRITE to occur independ ent of the BWE
and BWn lines and must meet the set-up and hold times around the rising edge of CLK.
4K 89 CLK Input-
Synchronous
Clock: This signal registers the addresses, data, chip enables , write control, and burst c ontrol inputs on its ris­ing edge. All synchron ous inp uts m ust m eet set-u p and hold times around the clock’s rising edge.
4E 98 CE
Input-
Synchronous
Chip Enable: Th is active LO W input is used to enable the device and to gate ADSP
.
2B 97 CE
2
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
- (not availab le for PBGA)
92 (for TA Version
only)
CE
2
Input-
Synchronous
Chip Enable: Th is active LO W input is used to enable the device. Not available for B and T package versions.
4F 86 OE
Input Output Enable: This a ctive LO W asynch ronous input en-
ables the data output drivers.
4G 83 ADV
Input-
Synchronous
Address Advance : This activ e LO W input is us ed to con­trol the internal burst co unter. A HIGH on this pin gener­ates wait cycle (no address advance).
4A 84 ADSP
Input-
Synchronous
Address Status Processo r: This active LO W input, along with CE
being LOW, causes a new external address to be registered and a READ cycle i s initiated using the new address.
4B 85 ADSC
Input-
Synchronous
Address Status Controller: This active LOW input caus­es the device to be deselected or selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
3R 31 MODE Input-
Static
Mode: This input sele cts the b urst seq uence. A L OW on this pin selects Linear Burst. A NC or HIGH on this pin selects Interleaved Burst.
7T 64 ZZ Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power consumption standby mode. For normal opera­tion, this input has to be e ither LOW or NC (N o Connect).
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
6
(a) 6P, 7P, 7N, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G,
6F, 6E, 7E, 7D, 6D,
(c) 2D , 1D, 1E, 2E, 2F,
1G, 2G, 1H, 2H,
(d) 1K, 2K, 1L, 2L,
2M, 1N, 2N, 1P, 2P
(a) 51, 52, 53, 56,
57, 58, 59, 62, 63
(b) 68, 69, 72, 73,
74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8,
9, 12, 13
(d) 18, 19, 22, 23,
24, 25, 28, 29, 30
DQa DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First By te i s DQa. Se co nd By te i s DQb. Third Byt e is DQc. F ourth Byte is DQd. Input data must meet set-up and hol d times around the rising edge of CLK.
2U 3U 4U
38 39 43
for B and T v ersion
TMS
TDI
TCK
Input IEEE 1149.1 test inputs. LVTTL-level inputs. Not avail-
able for TA package version.
5U 42
for B and T v ersion
TDO Output IEEE 1149.1 test output. LVTTL-level output. Not avail-
able for TA package version.
4C, 2J, 4J, 6J, 4R 15, 41, 65, 91 V
CC
Supply Core power Supply: +3.3V –5% and +10%
3D , 5D, 3E, 5E, 3F , 5F,
3H, 5H, 3K, 5K, 3M,
5M, 3N, 5N, 3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
V
SS
Ground Ground: GND.
1A, 7A, 1F, 7F , 1J , 7J,
1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
V
CCQ
I/O Supply Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 4D,
3J, 5J, 4L, 1R, 5R,
7R, 1T, 2T, 6T, 6U
14, 16, 66
38, 39, 42 for TA
Version
NC - No Connect: These sig nals are not internally conne cted.
User can leave it floating or connect it to V
CC
or VSS.
256K X 36 Pin Descriptions
(continued)
X36 PBGA Pins X36 QFP Pins Name Type Description
512K X 18 Pin Descriptions
X18 PBGA Pins X18 QFP Pins Name Type Description
4P
4N 2A, 3A, 5A, 6A, 3B, 5B, 6B, 2C, 3C, 5C,
6C, 2R, 6R, 2T, 3T,
5T, 6T
37 36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
92 (T Version)
43 (TA Version)
A0 A1
A
Input-
Synchronous
Addresses: These inputs are registered and must meet the set up and hold t imes ar ound the rising ed ge of C LK. The burst counter generates internal addresses associ­ated with A0 and A1, during burst cycle and wait cycle.
5L
3G
93 94
BWa BWb
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BW a
controls DQa. BWb controls DQb . Data I/O ar e high impedanc e if either of these inputs are LOW, conditioned by BWE
be-
ing LOW.
4M 87 BWE
Input-
Synchronous
Write Enable: This active LOW input gates byte write op­erations and mus t meet the set-up and hold times aro und the rising edge of CLK.
4H 88 GW
Input-
Synchronous
Global Write: This active LOW input allows a full 18-bit WRITE to occur inde pendent o f the BWE
and WEn lines and must meet the set-up and hold times around the ris­ing edge of CLK.
4K 89 CLK Input-
Synchronous
Clock: This signa l registers the addres ses, data, ch ip en­ables, write control and burst control inputs on its rising edge. All sync hronous inputs m ust mee t set- up and h old times around the clock’s rising edge.
4E 98 CE
Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device and to gate ADSP
.
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
7
2B 97 CE2 Input-
Synchronous
Chip Enable: This active HIGH input is use d to enable the device.
- (not available for PBGA)
92 (for TA Versio n
only)
CE2 Input-
Synchronous
Chip Enable: This active LOW input is used to enable the device. Not available for B and T package versions.
4F 86 OE
Input Output Enable: Thi s activ e LOW asynchronous input en-
ables the data output drivers.
4G 83 ADV
Input-
Synchronous
Address Adva nc e: T his ac tive LOW input is used to c on­trol the internal burst counter. A HIGH on this pin gener­ates wait cycle (no address advance).
4A 84 ADSP
Input-
Synchronous
Address Status Processor: This act ive LO W in put, along with CE
being LOW , ca uses a new ex ternal address to be registered and a READ cycle is initiated using the new address.
4B 85 ADSC
Input-
Synchronous
Address Status Cont roller: This activ e LOW input causes device to be de selected or se lected along with ne w e xter­nal address to be registere d. A READ or WRI TE cycle i s initiated depending upon write control inputs.
3R 31 MODE Input-
Static
Mode: This inpu t se lec ts th e burst sequence. A LOW on this pin selects Linear Burst. An NC or HIGH on this pi n selects Interleaved Burst.
7T 64 ZZ Input-
Asynchronous
Snooze: This active HIGH input puts the device in low power consump tion standby mode. F or normal operation, this input has to be either LOW or NC (No Connect).
(a) 6D, 7E, 6F, 7G,
6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P
(a) 58, 59, 62, 63,
68, 69, 72, 73, 74
(b) 8, 9, 12, 13, 18,
19, 22, 23, 24
DQa DQb
Input/
Output
Data Inputs/Outputs: Lo w Byte is DQa. High Byte is DQb. Input data must meet set up and hold times around the rising edge of CLK.
2U 3U 4U
38 39 43
for B and T v ersion
TMS
TDI
TCK
Input IEEE 1149.1 test inputs. LVTTL-level inputs . Not available
for TA package version.
5U 42
for B and T v ersion
TDO Output IEEE 1149.1 test output. LVTTL-level output. Not avail-
able for TA package version.
4C, 2J, 4J, 6J, 4R 15, 41,65, 91 V
CC
Supply Core power Supply: +3.3V –5% and +10%
3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M, 3N,
5N, 3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67, 71,
76, 90
V
SS
Ground Ground: GND.
1A, 7A, 1F , 7 F , 1J, 7J ,
1M, 7M, 1U, 7U
4, 11, 20, 27, 54,
61, 70, 77
V
CCQ
I/O Supply Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 2D,
4D, 7D, 1E, 6E, 2F,
1G, 6G, 2H, 7H, 3J,
5J, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P,
6P, 1R, 5R, 7R, 1T,
4T, 6U
1–3, 6, 7, 14, 16, 25, 28–30, 51–53, 56, 57, 66, 75, 78,
79, 80, 95, 96
38, 39, 42 for TA
Version
NC - No Connect: These signals are not internally connected.
User can leave it floating or connect it to V
CC
or VSS.
512K X 18 Pin Descriptions
(continued)
X18 PBGA Pins X18 QFP Pins Name Type Description
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
8
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW. For X36 product, WRITE
= L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For X18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa
enables write to DQa. BWb enables write to DQb. BWc enables write to DQ c. BWd ena bles wri te to DQd.
5. All inputs except OE must meet set up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.l
7. For a write operation following a read operation, OE
must be HI GH befo re the in put data re quired set -up time plus High- Z time f or OE and staying HIGH throughout
the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP
LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for
the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Burst Address Table (MODE = NC/VCC)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00 A...A01 A...A10 A...A11 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10
Truth Table
[3, 4, 5, 6, 7, 8, 9]
Operation Address Used CE CE2 CE2 ADSP ADSC ADV WRITE OE CLK DQ
Deselected Cycle, Power Down None H X X X L X X X L-H High-Z Deselected Cycle, Power Down None L X L L X X X X L-H High-Z Deselected Cycle, Power Down None L H X L X X X X L-H High-Z Deselected Cycle, Power Down None L X L H L X X X L-H High-Z Deselected Cycle, Power Down None L H X H L X X X L-H High-Z READ Cycle, Begin Burst External L L H L X X X L L-H Q READ Cycle, Begin Burst External L L H L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H H L X L X L-H D READ Cycle, Begin Burst External L L H H L X H L L-H Q READ Cycle, Begin Burst External L L H H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X H H L H L L-H Q READ Cycle, Continue Burst Next X X X H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X X H L H L L-H Q READ Cycle, Continue Burst Next H X X X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X H H L L X L-H D WRITE Cycle, Continue Burst Next H X X X H L L X L-H D READ Cycle, Suspend Burst Current X X X H H H H L L-H Q READ Cycle, Suspend Burst Current X X X H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X X H H H L L-H Q READ Cycle, Suspend Burst Current H X X X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X X H H L X L-H D
CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18
PRELIMINARY
9
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a man ner consi stent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but d oes not im plement al l of th e func tions re quired for IEEE 1149.1 compliance. Certain functions have been modi­fied or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state m achin e tha t cont rols t he TAPs operation) and can be expected to function in a manner that does not conflict with the o pera tion of de vice s with IEEE Stan­dard 1149.1 compliant TAPs. The TAP operates using LVTTL/ LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possib le to use this de v ice witho ut using the JTAG feature . To disable t he TAP contro ller without i nterfering with no rmal operation of the de vice , TCK shou ld be tied LO W (V
SS
) to pre­vent cloc king the d e vice . TDI and TMS ar e internally pulled up and may be unconnected. They may alternately be pulled up to V
CC
through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere w ith the ope r ati on of the device.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outp uts propagate fr om the f alling edge of TCK.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowab le to lea ve this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
TDI - Test Data In (INPUT)
The TDI input is samp led on the rising edge o f TCK. This is the input side of the se rial registers pl aced betwe en TDI and TDO . The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruc­tion that is currentl y loaded in the TAP instruction register (ref er to Figure 1, TAP Controller State Diagram). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up inter nally, resulting in a logic HIGH level. TDI is connected to th e M ost Si gn ific an t Bi t (M SB) o f a n y re g­ister. (See Figure 2.)
TDO - Test Data Out (OUTPUT)
The TDO output pin i s use d to seri all y clo ck data-out from the registers. The output that is active depending on the state of the TAP state machine (ref er to Figure 1, TAP Controller State Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial regi sters placed be­tween TDI and TDO . TDO is conne cted to the Least Significa nt Bit (LSB) of any register. (See Figure 2.)
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST
, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (V
CC
) for five rising edges of TCK and pre-loads the instruction reg­ister with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only.
At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the sequences of ones and z eros inpu t to the TMS pin a s the TC K is strobed. Each of the TAPs registers are serial shift register s that capture serial input data on the rising edge of TCK and push serial data out on subseque nt f alling edge of TCK. Whe n a register is selected, it is connected between the TDI and TDO pins.
Instruction Register
The instruction register holds the instructions that are execut­ed by the TAP controller when it is moved into the run test/idl e or the various data register states. The instructions are three bits long. The register c an be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automaticall y preloaded with th e IDCODE instruc­tion upon powe r-up or whenever the controller is placed in th e test-logic reset state. When the TAP controller is in the Cap­ture-IR state, the two least si gnifican t bits of the serial instruc­tion register are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum del ay. The bypass register is set LOW (V
SS
) when the BYPASS instruction is executed.
Note:
10. For the X18 product, there are only BWa
and BWb.
Partial Truth Table for READ/WRITE
[10]
Function GW BWE BWa BWb BWc BWd
READ H H X X X X READ H L H H H H WRITE one byte H L L H H H WRITE all bytes H L L L L L WRITE all bytes L X X X X X
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