Cypress Semiconductor CY7C1049-20VI, CY7C1049-20VC, CY7C1049-17VC, CY7C1049-15VC, CY7C1049L-25VC Datasheet
...
049
PRELIMINARY
512K x 8 Static RAM
Features
• High speed
= 15 ns
—t
AA
• Low active pow er
—1210 mW (max.)
• Low CMOS standby power (Commercial L ver sion)
—2.75 mW (max.)
• 2.0V Data Retention (400 µW at 2.0V retention)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
and OE f eatures
Functional Description
The CY7C1049 is a high-performance CMOS static RAM organized as 524,288 words by 8 bit s. Easy memory expansion
Logic Block Diagram Pin Configuration
is provided b y an activ e LOW chip enab le (CE
output enable (OE
), and three-stat e drivers. Writing t o the device is accomp lished by taki ng chip enable (CE
able (WE
I/O
pins (A
) inputs LO W . Data on the eight I/O pins ( I/O0 through
) is then written into the location specified on the address
7
through A18).
0
Reading from the device is accomplished by taking chip enable (CE
able (WE
) and output enabl e (OE) LOW while f or cing write en-
) HIGH. Under these conditions, the contents of the
memory location specified by the address pins will appear on
the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O7) are placed in a
0
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE
LOW, and WE LOW).
The CY7C1049 is available in a stan dard 400-mil-wide 36-pin
SOJ package with center power and ground (revolutionary)
pinout.
SOJ
Top View
CY7C1049
), an active LO W
) and write en-
WE
OE
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1049–1
0
1
2
3
4
5
6
7
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
A
A
ROW DECODER
8
9
10
512K x 8
ARRAY
COLUMN
DECODER
11
12
A
A13A
14
ACEA
SENSE AMPS
POWER
DOWN
15
16
17
18
A
A
A
I/O
V
GND
I/O
I/O3
WE
1
CC
2
A
5
A
6
A
7
A
8
A
9
36
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
NC
35
A
18
34
A
17
33
A
16
32
A
15
31
OE
30
I/O
7
29
I/O
6
28
GND
27
V
CC
26
I/O
5
25
I/O
4
24
A
14
23
A
13
22
A
12
21
A
11
20
A
10
19
NC
1049–2
Selection G uide
7C1049-12 7C1049-15 7C1049-17 7C1049-20 7C1049-25
Maximum Access Time (ns) 12 15 17 20 25
Maximum Operat ing Current (mA) 240 220 195 185 180
Maximum CMOS Standby
Current (mA)
Shaded areas contain advance information.
Com’l 888 8 8
Com’l L 0.5 0.5 0.5 0.5 0.5
Ind’l 999 9 9
Military 10 10
Cypress Semiconductor Corporation
• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1996 – Re vised April 6, 1998
PRELIMINARY
Maximum Ratings
(Abov e which the useful life ma y be impaired. For user guidelines, not tested.)
Storage Temperature ...... ....... ... .. ........ .. .....–65°C to +1 5 0°C
Ambient Temperature with
Power Applied ............................................. –55°C to +12 5°C
Supply Voltage on VCC to Relative GND
DC Voltage Applied to Outputs
in High Z State
DC Input Voltage
[1]
....................................–0.5V to VCC + 0.5V
[1]
.................................–0.5V to VCC + 0.5V
Current into Outputs (LOW) .........................................20 mA
Electrical Characteristics
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Shaded areas contain advance information.
Notes:
1. V
2. T
A
Output HIGH V ol ta ge VCC = Min., IOH = –4.0 mA 2.4 2.4 2.4 V
Output LO W Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V
Input HIGH Voltage 2.2 V
Input LOW Voltage
[1]
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supply Current
Automatic CE
P ower-Down Current
—TTL Inputs
Automatic CE
P ower-Down Current
—CMOS Inputs
(min.) = –2.0V f or pulse durati ons o f les s than 2 0 ns.
IL
is the “i nstan t on” case temperature.
[1]
....–0.5V to +7.0V
Over the Operating Range
CC
GND < V
Output Disabled
VCC = Max.
f = f
MAX
Max. V
VIN > VIH or
V
< VIL, f = f
IN
OUT
= 1/t
, CE > V
CC
< VCC,
,
RC
IH
MAX
Max. VCC,
CE
> VCC – 0.3V,
V
> VCC – 0.3V,
IN
or V
< 0.3V, f=0
IN
Com’l
Com’lL
Ind’l
Military
CY7C1049
Static Discharge Voltage ............................ .. .............>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Ambient
Range
Temperature
Commercial 0°C to +70°C 4.5V–5.5V
Industrial –40°C to +85°C
Military –55°C to +125°C
7C1049-12 7C1049-15 7C1049-17
Min. Max. Min. Max. Min. Max. Unit
2.2 V
CC
+ 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.3 V
–1 +1 –1+1–1+1µA
–1 +1 –1+1–1+1µA
240 220 195 mA
40 40 40 mA
888mA
0.5 0.5 0.5 mA
999mA
10 10 10 mA
CC
+ 0.3
[2]
2.2 V
V
CC
CC
+ 0.3
V
2
Electrical Characteristics
PRELIMINARY
Over the Op erating Range (continued)
CY7C1049
Test Conditions 7C1049-20 7C1049-25
Parameter Description Min. Max. Min. Max. Unit
V
V
V
V
I
IX
I
OZ
I
CC
I
SB1
I
SB2
OH
OL
IH
IL
Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V
Input HIGH Voltage 2.2 V
+ 0.3
Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage
Current
VCC Operating
Supp ly Cur r ent
Automatic CE
Power-Down Current
—TTL Inputs
Automatic CE
Power-Down Current
—CMOS Inputs
[1]
GND < V
Output Disabled
VCC = Max.
f = f
Max. V
VIN > VIH or
V
IN
Max. VCC,
CE
V
IN
or V
CC
< VCC,
OUT
,
= 1/t
MAX
< VIL, f = f
, CE > V
CC
RC
MAX
> VCC – 0.3V,
> VCC – 0.3V,
< 0.3V, f=0
IN
–0.3 0.8 –0.3 0.8 V
–1+1–1+1µA
–1+1–1+1µA
IH
Com’l88mA
Com’lL 0.5 0.5 mA
Ind’l99mA
CC
2.2 V
185 180 mA
40 40 mA
CC
0.3
+
Military 10 10 mA
V
Capacitance
[3]
Parameter Description T est Conditions Max. Unit
C
IN
C
OUT
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz,
V
= 5.0V
I/O Capacitance 8 pF
CC
8pF
3
PRELIMINARY
CY7C1049
4
PRELIMINARY
CY7C1049
AC Test Loads and Waveforms
R1 481
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to: VENIN EQUIVALENT
OUTPUT
(a)
THÉ
Switching Characteristics
Ω
167
OUTPUT
R2
255
Ω
Ω
[4]
Over the Operating Range
5V
INCLUDING
JIG AND
SCOPE
1.73V
5 pF
(b)
R1 481
Ω
1049–3
R2
255
3.0V
GND
Ω
3ns
≤
7C1049-12 7C1049-15 7C1049-17
Parameter Description
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Shaded areas contain advance information.
Notes:
4. T es t conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL/IOH
5. t
HZOE
6. At any given temperature and voltage condition, t
7. The internal write time of the memory is defined by the overlap of CE
these signals can terminate the write. The input da ta s et-up an d hold t iming should be ref e renced to th e leading e dge of the s ignal t hat t erminates the write .
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t
Read Cycle Time 12 15 17 ns
Address to Data Valid 12 15 17 ns
Data Hold from Address Change 3 33ns
CE LOW to Data Valid 12 15 17 ns
OE LOW to Data Valid 678ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[6]
[6]
[5, 6]
[5, 6]
0 00ns
677ns
3 33ns
677ns
CE LOW to Power-Up 0 00ns
CE HIGH to Power-Down 12 15 17 ns
[7,8]
Wr ite Cycle Tim e 12 15 17 ns
CE LOW to Write End 10 12 12 ns
Address Set-Up to Write End 10 12 12 ns
Address Hold from Write End 0 00ns
Address Set-Up to Write Start 0 00ns
WE Pulse Widt h 10 12 12 ns
Data Se t- U p to Write End 7 88ns
Data Hold from Write End 0 00ns
WE HIGH to Low Z
WE LO W to Hi gh Z
and 30-pF load ca pacitanc e.
, t
HZCE
, and t
are specified wi th a loa d capac itance of 5 pF as i n part (b) of A C Test Loads. Transition is measured ±500 mV from steady- state v ol tage .
HZWE
[6]
[5, 6]
HZCE
is less than t
3 33ns
678ns
, t
LZCE
is less than t
HZOE
LOW, and W E LOW. CE and WE must be LOW to ini tiat e a w rite, and t he tr ansiti on of eithe r of
LZOE
, and t
HZWE
is less tha n t
HZWE
and tSD.
ALL INPUT PULSES
90%
10%
for any given de v ice.
LZWE
90%
10%
1049–4
3
ns
≤
5
PRELIMINARY
[4]
Switching Characteristics
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time 20 25 ns
Address to Data Valid 20 25 ns
Data Hold from Address Change 3 5 ns
CE LOW to Data Valid 20 25 ns
OE LOW to Data Valid 8 10 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 0 ns
CE HIGH to Powe r- Down 20 25 ns
[7]
Write Cycle Time 20 25 ns
CE LOW to Write End 13 15 ns
Address Set-Up to Write End 13 15 ns
Address Hold from Write End 0 0 ns
Address Set-Up to Write Start 0 0 ns
WE Pulse Width 13 15 ns
Data Set-Up to Write End 9 10 ns
Data Hold from Write End 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
Over the Operating Range (continued)
[6]
[5, 6]
[6]
[5, 6]
[6]
[5, 6]
CY7C1049
7C1049-20 7C1049-25
UnitMin. Max. Min. Max.
00ns
810ns
35ns
810ns
35ns
810ns
Data Rete n ti o n C h ar acterist ic s
Over the Operating Range
Parameter Description Conditions
V
DR
I
CCDR
[3]
t
CDR
[9]
t
R
Notes:
9. t
< 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds.
r
10. No input may exceed V
VCC for Data Retention 2.0 V
Data Retention Current Com’lLVCC = VDR = 3.0V,
CE
Ind’l1mA
Military 2 mA
> VCC – 0.3V
V
> VCC – 0.3V or VIN < 0.3 V
IN
Chip Deselect to Data Retention Time 0 ns
Operation Recovery Time t
+ 0.5V.
CC
6
[10]
Min. Max Unit
200 µA
RC
ns
Data Retention Waveform
V
CC
CE
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
Read Cycle No. 2 (OE Control led)
[11, 12]
PREVIOUS DATA VALID DATA VALID
PRELIMINARY
t
CDR
t
AA
[12, 13]
t
OHA
DATA RETENTION MODE
VDR> 2V
t
RC
CY7C1049
3.0V3.0V
t
R
1049–5
1049–6
ADDRESS
CE
t
ACE
OE
t
DOE
t
t
LZCE
LZOE
50%
DAT A OUT
V
CC
SUPPLY
HIGH IMPEDANCE
t
PU
CURRENT
Notes:
11. Device is continuously selected. OE
12. WE
is HIGH f or r ead cycle .
13. Address valid prior to or coincident with CE transition LOW .
, CE = VIL.
t
RC
t
HZOE
t
DATA VALID
HZCE
t
PD
HIGH
IMPEDANCE
ICC
50%
ISB
1049–7
7
PRELIMINARY
Switching Waveforms
Write Cycle No. 1 (CE
ADDRESS
CE
WE
DATA I/O
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)
(continued)
Controlled )
[14, 15]
t
SA
t
AW
t
WC
[14, 15]
t
WC
t
PWE
t
SCE
t
SCE
t
SD
DATA VALID
CY7C1049
t
HA
t
HD
1049–8
ADDRESS
t
SCE
CE
t
AW
t
SA
t
PWE
WE
OE
t
SD
DATA I/O
Notes:
14. Data I/O is high impedance if OE
15. If CE
16. During this period the I/Os are in the output state and input signals should not be applied.
goes HIGH sim ultaneous ly with WE going HI GH, the output rem ains in a high-i mpedance state.
NOTE 16
= VIH.
t
HZOE
DATAINVALID
t
HA
t
HD
1049–9
8
Switching Waveforms
Write Cycle No. 3 (WE
ADDRESS
CE
WE
DATA I/O
Controlled, OE LOW)
16
NOTE
(continued)
t
SA
PRELIMINARY
[15]
t
AW
t
HZWE
t
SCE
t
WC
t
PWE
t
SD
DATA VALID
t
HA
t
LZWE
CY7C1049
t
HD
1049–10
Ordering Information
Speed
(ns)
Ordering Code
15 CY7C1049-15VC V36 36-Lead (400-Mil) Molded SOJ Commercial
CY7C1049L-15VC V36 36-Lead (400-Mil) Molded SOJ
17 CY7C1049-17VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049L-17VC V36 36-Lead (400-Mil) Molded SOJ
20 CY7C1049-20VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049L-20VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049-20VI V36 36-Lead (400-Mil) Molded SOJ Industrial
CY7C1049L-20VI V36 36-Lead (400-Mil) Molded SOJ
CY7C1049-20VM V36 36-Lead (400-Mil) Molded SOJ Military
CY7C1049L-20VM V36 36-Lead (400-Mil) Molded SOJ
25 CY7C1049-25VC V36 36-Lead (400-Mil) Molded SOJ Commercial
CY7C1049L-25VC V36 36-Lead (400-Mil) Molded SOJ
CY7C1049-25VI V36 36-Lead (400-Mil) Molded SOJ Industrial
CY7C1049L-25VI V36 36-Lead (400-Mil) Molded SOJ
CY7C1049-25VM V36 36-Lead (400-Mil) Molded SOJ Military
CY7C1049L-25VM V36 36-Lead (400-Mil) Molded SOJ
Shaded areas contain advance information.
Document #: 38–00563–B
Package
Name
Package Type
Operating
Range
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it conv ey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
PRELIMINARY
36-Lead (400-Mil) Molded SOJ V36
CY7C1049
10
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