Cypress Semiconductor CY7C1021B-12ZI, CY7C1021B-12ZC, CY7C1021B-12VI, CY7C1021B-12VC, CY7C10211BL-10ZC Datasheet
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0211B
CY7C1021B/
CY7C10211B
64K x 16 Static RAM
Features
• High speed
—t
= 10, 12, 15 ns
AA
• CMOS for optimum speed/power
• Low active power
—825 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1021B/10211B is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
specified on the address pins (A
through I/O16) is written into the location
9
through A15).
0
Reading from the device is accomplished by taking Chip Enable (CE
Enable (WE
) and Output Enable (OE) LOW while f orcing the Write
) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
then data from memory will appear on I/O
truth table at the back of this data sheet for a com plete descrip-
to I/O8. If Byte High Enable (BHE) is LOW,
1
to I/O16. See the
9
tion of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
through I/O16) are placed in a
1
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1021B/10211B is available in standard 44-pin
TSOP Type II and 400-mil-wide SOJ packages. Customers
should use part number CY7C10211B when ordering parts
with 10ns t
, and CY7C1021B when ordering 12 and 15n s taa.
aa
0
Logic Block Diagram
DATA IN DRIVERS
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
512 X 2048
COLUMN DECODER
8
A
A
9
A10A11A
I/O
–I/O
1
8
SENSE AMPS
I/O9–I/O
16
BHE
WE
12
14
15
A13A
A
CE
OE
BLE
1021B-1
Pin Configuration
SOJ / TSOP II
Top View
44
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
WE
A
A
A
A
NC
A
A
A
A
A
CE
CC
SS
15
14
13
12
1
4
2
3
3
2
4
1
5
0
6
7
1
8
2
9
3
10
4
11
12
13
5
14
6
15
7
16
8
17
18
19
20
21
22
A
5
43
A
6
42
A
7
41
OE
40
BHE
39
BLE
38
I/O
37
I/O
36
I/O
35
I/O
34
V
SS
33
V
CC
32
I/O
31
I/O
30
I/O
29
I/O
28
NC
27
A
8
26
A
9
25
A
10
A
24
11
23
NC
1021B-2
16
15
14
13
12
11
10
9
Selection Guide
7C10211B-10 7C1021B-12 7C1021B-15
Maximum Access Time (ns) Commercial 10 12 15
Maximum Operating Current (mA) Commercial 150 140 130
Maximum CMOS Standby Current (mA) Commercial 10 10 10
L0.50.5 0.5
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05145 Rev. ** Revised September 6, 2001
CY7C1021B/
Maximum Ratings
(Above which the useful life may be impai red. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High Z State
[1]
DC Input Voltage
to Relative GND
CC
......................................–0.5V to VCC+0.5V
[1]
..................................–0.5V to VCC+0.5V
[1]
....–0.5V to +7.0V
Electrical Characteristics Ov er the Op erat ing Range
Parameter Description
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
[1]
Voltage
Input Load
Current
Output
Leakage
Current
I
I
OS
CC
Output Short
Circuit
[3]
Current
VCC
Operating
Supply
Current
I
SB1
Automatic CE
Power-Down
Current
—TTL Inputs
I
SB2
Automatic CE
Power-Down
Current
—CMOS
Inputs
VCC = Min.,
IOH = –4.0 mA
VCC = Min.,
IOL = 8.0 mA
GND < VI < V
GND < VI < VCC,
Output Disabled
VCC = Max.,
V
VCC = Max.,
I
OUT
f = f
Max. VCC,
CE
VIN > VIH or
VIN < VIL,
f = f
Max. VCC,
CE
V
VCC – 0.3V,
or V
0
Test
Conditions
= GND
OUT
= 0 mA,
= 1/t
MAX
> V
IH
MAX
>
– 0.3V , VIN >
CC
< 0.3V , f =
IN
CC
RC
L0.50.5 0.5 mA
CY7C10211B
Current into Outputs (LOW)........................................ 20 mA
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Operating Range
Range
Temperature
Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%
Ambient
7C10211B-10
7C1021B-12 7C1021B-15
2.4 2.4 2.4 V
0.4 0.4 0.4 V
2.2 6.0 2.2 6.0 2.2 6.0 V
−0.5 0.8 –0.5 0.8 –0.5 0.8 V
−1+1–1 +1 –1 +1 µA
−1+1–1 +1 –1 +1 µA
−300
–300 –300 mA
150 140 130 mA
40 40 40 mA
10 10 10 mA
[2]
V
CC
UnitMin. Max. Min. Max. Min. Max.
Document #: 38-05145 Rev. ** Page 2 of 11
CY7C1021B/
CY7C10211B
Capacitance
[4]
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Input Capacitance TA = 25°C, f = 1 MHz,
= 5.0V
V
Output Capacitance 8 pF
CC
8 pF
AC Test Loads and Waveforms
5 pF
(b)
R 481Ω
1021B-3
1.73V
R2
255
3.0V
GND
Ω
Rise Time: 1 V/ns Fall Time:1 V/ns
ALL INPUT PULSES
90%
10%
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
Equivalent to:
30 pF
R 481Ω
(a)
THÉVENIN
EQUIVALENT
OUTPUT
R2
255
Ω
OUTPUT
5V
INCLUDING
JIG AND
SCOPE
167
30 pF
90%
10%
1021B-4
Document #: 38-05145 Rev. ** Page 3 of 11
CY7C1021B/
CY7C10211B
Switching Characteristics
[5]
Over the Operating Range
7C10211B-10 7C1021B-12 7C1021B-15
Parameter Description
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Notes:
(min.) = –2.0V for pulse durati ons of l ess than 2 0 ns.
1. V
IL
is the “Instant On” case temperatur e.
2. T
A
3. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
4. Tested initially and after any design or process changes that may affect these parameters.
5. T est conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V, and output loading of the specified
6. At any given temperature and voltage condition, t
7. t
8. The internal write time of the memory is defined by the overlap of CE
and 30-pF load c apacitan ce.
I
OL/IOH
, t
HZOE
and the transition of these sig nals can t erminate the writ e. The input data set-up and hold timing s hould be refere nced to the leading edge of the signal t hat terminates the write.
Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 10 12 15 ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
[6]
[6, 7]
[6]
[6, 7]
0 0 0 ns
5 6 7 ns
3 3 3 ns
5 6 7 ns
CE LOW to Power-Up 0 0 0 ns
CE HIGH to Power-Down 10 12 15 ns
Byte Enable to Data Valid 5 6 7 ns
Byte Enable to Low Z 0 0 0 ns
Byte Disable to High Z 5 6 7 ns
[8]
Write Cycle Time 10 12 15 ns
CE LOW to Write End 8 9 10 ns
Address Set-Up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-Up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-Up to Write End 5 6 8 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z
[6]
[6, 7]
3 3 3 ns
5 6 7 ns
Byte Enable to End of Write 7 8 9 ns
HZBE
, t
HZCE
, and t
is less than t
are specified w ith a load ca pacit ance of 5 pF as in part (b ) of AC Test L oads. T ransiti on i s measured ±500 mV from steady-state voltage.
HZWE
HZCE
, t
LZCE
is less than t
HZOE
LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
LZOE
, and t
HZWE
is less than t
for any given device.
LZWE
UnitMin. Max. Min. Max. Min. Max.
Document #: 38-05145 Rev. ** Page 4 of 11
CY7C1021B/
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
Read Cycle No. 2
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
[9, 10]
PREVIOUS DATA VALID DATA VALID
Controlled)
(OE
HIGH IMPEDANCE
t
LZCE
t
PU
[10, 11]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
t
OHA
50%
t
RC
t
AA
t
RC
t
HZOE
DATA VALID
CY7C10211B
t
HZCE
t
HZBE
t
PD
HIGH
IMPEDANCE
1021B-5
I
ICC
CC
50%
I
ISB
SB
1021B-6
Notes:
9. Device is continuously selected. OE
10. WE
is HIGH for read cycle .
11. Address valid prior to or coincident with CE
, CE, BHE and/or BHE = VIL.
transition LOW .
Document #: 38-05145 Rev. ** Page 5 of 11
CY7C1021B/
Switching Waveforms (continued)
t
SA
[12, 13]
Write Cycle No. 1 (CE
ADDRESS
CE
WE
BHE, BLE
Controlled)
t
AW
t
WC
t
SCE
t
PWE
t
BW
CY7C10211B
t
HA
DATA I/O
Write Cycle No. 2 (BLEorBHE Controlled)
ADDRESS
t
BHE
,BLE
WE
CE
SA
t
AW
t
WC
t
BW
t
PWE
t
SCE
t
SD
t
HD
1021B-7
t
HA
t
SD
t
HD
DATA I/O
1021B-8
Notes:
12. Data I/O is high impedance if OE
13. If CE
goes HIGH simultaneousl y with WE going HIGH, the o utput remains in a hig h-imped ance stat e.
or BHE and/or BLE= VIH.
Document #: 38-05145 Rev. ** Page 6 of 11
CY7C1021B/
Switching Waveforms (continued)
Write Cycle No. 3
ADDRESS
CE
WE
BHE, BLE
DATA I/O
Controlled, LOW)
(WE
t
SA
t
AW
t
SCE
t
WC
t
BW
t
HZWE
t
PWE
t
SD
t
HD
CY7C10211B
t
HA
t
LZWE
Truth Table
CE OE WE BLE BHE I/O1–I/O
8
H X X X X High Z High Z Power-Down Standby (ISB)
L L H L L Data Out Data Out Read - All bits Active (ICC)
L H Data Out High Z Read - Lower bits only Active (ICC)
H L High Z Data Out Read - Upper bits only Active (ICC)
L X L L L Data In Data In Write - All bits Active (ICC)
L H Data In High Z Write - Lower bits only Active (ICC)
H L High Z Data In Write - Upper bits only Active (ICC)
L H H X X High Z High Z Selected, Outputs Disable d Active (ICC)
L X X H H High Z High Z Selected, Outputs Di sa ble d Active (ICC)
I/O9–I/O
16
Mode Power
1021B-10
Document #: 38-05145 Rev. ** Page 7 of 11
CY7C1021B/
Ordering Information
Speed
(ns) Ordering Code
10 CY7C10211B-10VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C10211B-10ZC Z44 44-Lead TSOP Type II Commercial
CY7C10211BL-10ZC Z44 44-Lead TSOP Type II Commercial
12 CY7C1021B-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1021B-12VI V34 44-Lead (400-Mil) Molded SOJ Industrial
CY7C1021BL-12VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1021B-12ZC Z44 44-Lead TSOP Type II Commercial
CY7C1021B-12ZI Z44 44-Lead TSOP Type II Industrial
CY7C1021BL-12ZC Z44 44-Lead TSOP Type II Commercial
15 CY7C1021B-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1021B-15VI V34 44-Lead (400-Mil) Molded SOJ Industrial
CY7C1021BL-15VC V34 44-Lead (400-Mil) Molded SOJ Commercial
CY7C1021B-15ZC Z44 44-Lead TSOP Type II
CY7C1021B-15ZI Z44 44-Lead TSOP Type II Industrial
CY7C1021BL-15ZC Z44 44-Lead TSOP Type II
Package
Name Package Type
Commercial
Commercial
CY7C10211B
Operating
Range
Document #: 38-05145 Rev. ** Page 8 of 11
CY7C1021B/
Package Diagrams
44-Lead (400-Mil) Mo lded SOJ V3 4
CY7C10211B
51-85082-B
Document #: 38-05145 Rev. ** Page 9 of 11
CY7C1021B/
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
44-Pin TSOP II Z44
CY7C10211B
51-85087-A
Document #: 38-05145 Rev. ** Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. No r does it convey or imply any license under patent or other rights. Cypress Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assume s all risk of such use and in doi
CY7C1021B/
Document Title: CY7C1021B / CY7C10211B 64K x 16 Static RAM
Document Number: 38-05145
REV. ECN NO.
** 109889 09/22/01 SZV Change from Spec number: 38-00951 to 38-05145
Issue
Date
Orig. of
Change Description of Change
CY7C10211B
Document #: 38-05145 Rev. ** Page 11 of 11
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