Datasheet CY7C1019CV33-8VI, CY7C1019CV33-8VC, CY7C1019CV33-15ZI, CY7C1019CV33-15ZC, CY7C1019CV33-15VI Datasheet (Cypress Semiconductor)

CY7C1019CV33

128K x 8 St atic RAM

Features

• Pin and function compatible with CY7C1019BV33

• High speed
—t

= 8, 10, 12, 15 ns

AA

• CMOS for optimum speed/power

• Data retention at 2.0V

• Center power/ground pinout

• Automatic power-down when dese lec ted

• Easy memory expans ion with CE

and OE options

• Available in 32-pin TSOP II and 400-mil SOJ package

Functional Description

The CY7C1019CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is pr ovided by an ac tive LOW Chip Enable (CE

), an

active LOW Output Enable ( OE), and thre e-st ate driv ers. Th is

Logic Block Diagram

INPUT BUFFER

A

0

A

1

A

2

A

3

A

WE

CE

OE

4

A

5

A

6

A
A

ROW DECODER

7
8

512 x 256 x 8

ARRAY

COLUMN

DECODER

9

10

A

A

A11A13A

SENSE AMPS

POWER

DOWN

14

15

12

16

A

A

A

device has an aut omatic po wer-down fea ture that sig nificantl y
reduces power consumpt ion when deselected.

Writing to the device is accomplished by taking Chip Enable

) and Write Enable ( WE) inputs LOW. Data on the eight I/O

(CE
pins (I/O
specified on the address pins (A

through I/O7) is then written into the location

0

through A16).

0

Reading from the device is accomplished by taking Chip
Enable (CE
Enable (WE

) and Output Enable (OE) LOW while forcing Write

) HIGH. Unde r these co nditions, t he contents o f
the memory location s pecif ied by th e addres s pins will app ear
on the I/O pins.

The eight input/output pi ns (I/O
high-impedance state when the device is deselected (CE

through I/O7) are placed in a

0

HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW) .

The CY7C1019CV33 is available in a standard 32-pin TSOP
II and 400-mil-wide SOJ.

Configuration

Pin

SOJ/TSOP II

T op V ie w

32
31

30
29

28
27
26
25
24
23
22
21
20
19
18

17

A
A
A

A
OE

I/O
I/O

V
V
I/O
I/O

A
A

A
A

A

16
15
14

13

7
6

SS
CC

5
4

12
11

10
9

8

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

A

1

0

A

1

2

A

3

2

A

4

CE

I/O
I/O

V
V

I/O
I/O

WE

CC

SS

A
A
A

A

3

5
6

0

7

1

8
9
10

2
3

11
12

4

13

5

14

6

15
16

7

0

1

2

3

4

5

6

7

Selection Guide

7C1019CV33-8 7C1019CV33-10 7C1019CV33-12 7C1019CV33-15 Unit

Maximum Acces s Time 8 10 12 15 ns
Maximum Operating Current 85 80 75 70 mA
Maximum Standby Cu r r en t 5 5 5 5 mA

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05130 Rev. *D Revised December 16, 2002

CY7C1019CV33

Maximum Ratings

(Above which the us efu l l ife may be impaired. F or us er gui de­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage on V
DC Voltage Applied to Outputs

in High-Z State

[1]

DC Input Voltage

to Relative GND

CC

....................................–0.5V to VCC + 0.5V

[1]

.................................–0.5V to VCC + 0.5V

[1]

...–0.5V to + 4.6V

Electrical Characteristics Over the Operating Range

7C1019CV33-87C1019CV33

Parameter Description Test Conditions

V

V

V

V
I
I

I

I

I

I

OH

OL

IH

IL
IX
OZ

OS

CC

SB1

SB2

[2.]

Output HIGH Voltage VCC = Min.,

= –4.0 mA

I

OH

Output LOW Voltage VCC = Min.,

= 8.0 mA

I

OL

Input HIGH Voltage 2.0 V

Input LOW Voltage
Input Load Current GND < VI < V
Output Leakage

Current
Output Short

Circuit Current
VCC Operating

Supply Current

Automatic CE
Power-down Current
—TTL Inputs

Automatic CE
Power-down Current
—CMOS Inputs

[1]

GND < VI < VCC,
Output Disabled

VCC = Max.,
V

= GND

OUT

VCC = Max.,
I

= 0 mA,

OUT

f = f

MAX

Max. VCC, CE > V
VIN > VIH or

< VIL, f = f

V

IN

Max. VCC,

> VCC – 0.3V,

CE
VIN > VCC – 0.3V,
or V

IN

CC

= 1/t

RC

MAX

< 0.3V, f = 0

IH

Current into Outputs (LOW).........................................20 mA

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Latch-up Current......................................................>200 mA

Operating Range

Range

Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%

-10

2.4 2.4 2.4 2.4 V

0.40.40.40.4V

2.0 V

CC

+ 0.3

CC

+ 0.3

–0.3 0.8 –0.3 0.8 –0.3 0.8 –0.3 0.8 V

–1+1–1+1–1+1–1+1µA
–1+1–1+1–1+1–1+1µA

–300 –300 –300 –300 mA

85 80 75 70 mA

15 15 15 15 mA

5555mA

Ambient

Temperature V

7C1019CV33

-12

2.0 V

CC

+ 0.3

7C1019CV33

-15

2.0 V
+ 0.3

CC

UnitMin. Max. Min. Max. Min. Max. Min. Max.

CC

V

Capacitance

[3]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Notes:

1. V

(min.) = –2.0V for pulse durations of less than 20 ns.

IL

2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

3. Tested initially and after any design or process changes that may affect these parameters.

Input Capacitance TA = 25°C, f = 1 MHz,

= 5.0V

V

Output Capacitance 8 pF

CC

8pF

Document #: 38-05130 Rev. *D Page 2 of 8

CY7C1019CV33

AC Test Loads and Waveforms

8-ns devices:

OUTPUT

* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT

3.0V

GND

Rise Time: 1 V/ns

10%

Ω

Z = 50

ALL INPUT PULSES

90%

Switching Characteristics

Parameter Description

[4]

50Ω

1.5V

30pF*

(a)

90%

10%

(c)

[5]

Over the Operating Range

Fall Time: 1 V/ns

7C1019CV33-8 7C1019CV33-10 7C1019CV33-12

10-, 12-, 15-ns devices:

3.3V

OUTPUT

30 pF

High-Z characteristics:

3.3V

OUTPUT

5 pF

(b)

(d)

R 317Ω

R2

351Ω

R 317Ω

351

R2

Ω

7C1019CV33-15

UnitMin. Max. Min. Max. Min. Max. Min. Max.

Read Cycle

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

[8]

t

PU

[8]

t

PD

Write Cycle

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

t

HD

t

LZWE

t

HZWE

Notes:

4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin
load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.

6. t

7. At any given temperature and voltage condition, t

8. This parameter is guaranteed by design and is not tested.

9. The internal write time of the memory is defined by the overlap of CE
signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.

10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t

Read Cycle Time 8 10 12 15 ns
Address to Data Valid 8 10 12 15 ns
Data Hold from Address Change 3 3 3 3 ns
CE LOW to Data Valid 8 10 12 15 ns
OE LOW to Data Valid 5 5 6 7 ns
OE LOW to Low Z 0 0 0 0 ns

[7]

[6, 7]

[6, 7]

4567 ns

3333 ns

4567 ns

OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up 0 0 0 0 ns
CE HIGH to Power-Down 8 10 12 15 ns

[9, 10]

Write Cycle Time 8 10 12 15 ns
CE LOW to Write End78910 ns
Address Set-Up to Write End 7 8 9 10 ns
Address Hold from Write End 0 0 0 0 ns
Address Set-Up to Write Start 0 0 0 0 ns
WE Pulse Width 67810 ns
Data Set-Up to Write End 5 5 6 8 ns
Data Hold from Write End 0 0 0 0 ns
WE HIGH to Low Z
WE LOW to High Z

, t

HZCE

, and t

HZOE

are specified with a load cap acitance of 5 pF as in part (d) of AC Test Loads. Transit ion is measured ±500 mV from steady-state volt age.

HZWE

[7]
[6, 7]

HZCE

3333 ns

4567 ns

is less than t

, t

LZCE

is less than t

HZOE

LOW and WE LOW. CE and WE must be LOW to initiate a write, and the trans ition of any of thes e

LZOE

, and t

HZWE

is less than t

HZWE

and tSD.

for any given dev ice.

LZWE

Document #: 38-05130 Rev. *D Page 3 of 8

Switching Waveforms

Read Cycle No. 1

[11, 12 ]

ADDRESS

DATA OUT

PREVIOUS DATA VALID DATA VALID

t

OHA

CY7C1019CV33

t

RC

t

AA

Read Cycle No. 2 (OE Controlled)

ADDRESS

CE

OE

DATA OUT

V

CC

SUPPLY

HIGH IMPEDAN CE

t

LZCE

t

PU

CURRENT

Write Cycle No. 1 (CE Controlled)

ADDRESS

CE

[12, 13]

t

ACE

t

LZOE

[14, 15]

t

DOE

50%

t

RC

t

HZOE

t

DATA VALID

HZCE

t

PD

HIGH

IMPEDANCE

ICC

50%

ISB

t

WC

t

SCE

t

SA

t

t

AW

t

PWE

SCE

t

HA

WE

t

HD

DATA I/O

Notes:

11. Device is continuously selected. OE
is HIGH for read cycle.

12. WE

13. Address valid prior to or coincident with CE transition LOW .

14. Data I/O is high impedance if OE

15. If CE

goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.

, CE = VIL.

= VIH.

t

SD

DATA VALID

Document #: 38-05130 Rev. *D Page 4 of 8

Switching Waveforms (continued)

Write Cycle No. 2 (WE

ADDRESS

CE

Controlled, OE HIGH During Write)

CY7C1019CV33

[14, 15]

t

WC

t

SCE

t

SA

WE

OE

DATA I/O

NOTE 16

t

HZOE

Write Cycle No. 3 (WE Controlled, OE LOW)

ADDRESS

CE

t

SA

WE

[15]

t

AW

t

PWE

t

SD

t

HA

t

HD

DATAINVALID

t

WC

t

SCE

t

AW

t

PWE

t

HA

t

LZWE

t

HD

DATA I/O

NOTE

16

t

HZWE

t

SD

DATA VALID

Truth Table

CE OE WE I/O0–I/O

7

H X X High Z Power-Down Standby (ISB)
L L H Data Out Read Active (ICC)
L X L Data In Write Active (ICC)
L H H High Z Selected, Outputs Disabled Active (ICC)

Note:

16. During this period the I/Os are in the output state and input signals should not be applied.

Document #: 38-05130 Rev. *D Page 5 of 8

Mode Power

CY7C1019CV33

Ordering Information

Speed

(ns) Ordering Code

8 CY7C1019CV33-8VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019CV33-8VI V33 32-Lead 400-Mil Molded SOJ Industrial

10 CY7C1019CV33-10VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019CV33-10ZC ZS32 32-Lead TSOP II
CY7C1019CV33-10VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-10ZI ZS32 32-Lead TSOP II

12 CY7C1019CV33-12VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019CV33-12ZC ZS32 32-Lead TSOP II
CY7C1019CV33-12VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-12ZI ZS32 32-Lead TSOP II

15 CY7C1019CV33-15VC V33 32-Lead 400-Mil Molded SOJ Commercial

CY7C1019CV33-15ZC ZS32 32-Lead TSOP II
CY7C1019CV33-15VI V33 32-Lead 400-Mil Molded SOJ Industrial
CY7C1019CV33-15ZI ZS32 32-Lead TSOP II

Package Diagram

Package

Name Package Type

Operating

Range

32-lead (400-Mil) Molded SOJ V33

51-85033-A

51-85033-*B

Document #: 38-05130 Rev. *D Page 6 of 8

Package Diagram (continued)

CY7C1019CV33

32-lead

TSOP II ZS32

51-85095-**

All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-05130 Rev. *D Page 7 of 8

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Document History Page

Document Title: CY7C1019CV33 128K x 8 Static RAM
Document Number: 38-05130

REV. ECN NO.

** 109245 12/16/01 HGK New Data Sheet
*A 113431 04/10/02 NSL AC Test Loads split based on speed.
*B 115047 08/01/02 HGK Added TSOP II Package and I Temp. Improved I

*C 119796 10/11/02 DFP Updated standby current from 5 nA to 5 mA.
*D 123030 12/17/02 DFP Updated Truth Table to reflect single Chip Enable option.

Issue

Date

Orig. of
Change Description of Change

CY7C1019CV33

limits.

CC

Document #: 38-05130 Rev. *D Page 8 of 8