Cypress Semiconductor CY7C1011CV33-12ZI, CY7C1011CV33-12BVI, CY7C1011CV33-12BVC, CY7C1011CV33-12AI, CY7C1011CV33-12AC Datasheet
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CY7C1011CV33
128K x 16 St atic RAM
Features
written into the location specified on the address pins (A
through A16). If Byte High Enable (BHE) is LOW, then data
• Pin equivalent to CY7C1011BV33
• High speed
—t
= 10 ns
AA
• Low active power
—360 mW (max.)
• Data Retention at 2.0
• Automatic power-down when dese lec ted
• Independent control of upper and lower bits
• Easy memory expans ion with CE
and OE features
• Available in 44-pin TSOP II, 44-pin TQFP, and 48-ball
VFBGA
Functional Description
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE
Write Enable (WE
then data from the memory location specified by the address
pins will appear on I/O
LOW , then data from memory will app ear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH), the outp uts are d isabled (OE HIGH), the BHE and BLE
are disabled (BHE, BL E HIGH), or during a wri te operation (CE
through I/O15) is written into the location
8
through A16).
0
) and Output Enable (OE) LOW while forcing the
) HIGH. If Byte Low Enable (BLE) is LOW,
to I/O7. If Byte High Enable (BHE) is
0
through I/O15) are placed in a
0
LOW, and WE LOW).
The CY7C1011CV33 is a high-performance CMOS Static
RAM organized as 131,072 words by 16 bits.
Writing to the device is accomplished by taking Chip Enable
) and Write Enable (WE) inputs LOW. If Byte Low Enable
(CE
) is LOW, then data from I/O pins (I/O0 through I/O7), is
(BLE
The CY7C1011CV33 is available in a standard 44-pin TSOP
II package wi th center pow er and gro und pinou t, a 44-pin Thin
Plastic Quad Flatpac k (TQFP) , as wel l as a 48- ball f ine-pi tch
ball grid array (VFBGA) package.
Logic Block Diagram Pin Configuration
A
A
A
A
A
CE
CC
SS
WE
A
A
A
A
A
4
3
2
1
0
0
1
2
3
4
5
6
7
16
15
14
13
12
TSOP II
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
A
A
ROW DECODER
6
7
8
256K x 16
ARRAY
1024 x 4096
SENSE AMPS
I/O0 – I/O
I/O8 – I/O
7
15
I/O
I/O
I/O
I/O
V
COLUMN
DECODER
V
I/O
I/O
I/O
11
14
15
12
9
10
A
A
A
A13A
AAA
16
BHE
WE
CE
OE
I/O
BLE
A
5
A
6
A
7
OE
BHE
BLE
I/O
I/O
I/O
I/O
V
SS
V
CC
I/O
I/O
I/O
I/O
NC
A
8
A
9
A
10
A
11
NC
15
14
13
12
11
10
9
8
to I/O15. See
8
0
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05232 Rev. *B Revised October 10, 2002
CY7C1011CV33
Selection Guide
-10 -12 -15 Unit
Maximum Access Time 10 12 15 ns
Maximum Operating Current Comm’l908580mA
Ind’l 100 95 90
Maximum CMOS Standby Current Com’l/Ind’l101010mA
Pin Configurations
44-pin TQFP
(Top View)
13
11
9
10
A
A
OE
A
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
CC
I/O
11
I/O
10
I/O
9
I/O
8
NC
CE
I/O
I/O
I/O
I/O
V
V
I/O
I/O
I/O
I/O
CC
SS
14
A
16
A15A
12
A
A
1
0
1
2
3
4
5
6
7
1
BLE
I/O
I/O
V
SS
V
CC
I/O
I/O
NC
WE
8
9
14
15
0
1
A
A
A
48-ball VFBGA
2
OE
BHE
I/O
10
NC
I/O
11
I/O
12
I/O
13
NC
A
8
2
3
A
A4
(Top View)
4
3
A
A
0
1
A
A
4
3
A
A
5
6
A
7
A
NC
16
A
A
15
14
A
A
13
12
A
A
10
9
NC
A
5
A
CE
I/O
I/O
I/O
I/O
WE
A
5
A
8
6
7
A
A
6
NC
2
I/O
I/O
1
V
CC
3
V
4
I/O
5
I/O
NC
11
SS
A
B
0
C
2
D
E
F
6
G
7
H
Document #: 38-05232 Rev. *B Page 2 of 11
CY7C1011CV33
Maximum Ratings
(Above which the us efu l l ife may be impaired. For us er gui delines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on V
DC Voltage Applied to Outputs
in High-Z State
[2]
to Relative GND
CC
....................................–0.5V to VCC + 0.5V
DC Electrical Characteristics Over the Operating Range
Parameter Description Test Conditions
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
I
SB2
Capacitance
Output HIGH Voltage VCC = Min.,
Output LOW V o lt a ge VCC = Min.,
Input HIGH Voltage 2.0 V
Input LOW Voltage
[1]
Input Load Current GND < VI < V
Output Leakage Current GND < V
VCC Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
[2]
[2]
....–0.5V to +4.6V
= –4.0 mA
I
OH
= 8.0 mA
I
OL
CC
< VCC,
Output Disabled
VCC = Max., f = f
1/t
OUT
MAX
RC
Max. VCC, CE > V
VIN > VIH or
< VIL, f = f
V
IN
Max. V
> VCC – 0.3V,
CE
> VCC – 0.3V,
V
IN
or VIN < 0.3V, f = 0
CC
MAX
,
=
IH
[2]
DC Input Voltage
................................–0.5V to VCC + 0.5V
Current into Outputs (LOW).........................................20 mA
Operating Range
Range
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C
-10 -12 -15
2.42.42.4V
0.4 0.4 0.4 V
CC
+ 0.3
–0.3 0.8 –0.3 0.8 –0.3 0.8 V
–1+1–1+1–1+1µA
–1+1–1+1–1+1µA
Com’l908580mA
Ind’l 100 95 90 mA
40 40 40 mA
Com’l/
10 10 10 mA
Ind’l
Ambient
Temperature V
2.0 V
+ 0.3
CC
2.0 V
+ 0.3
CC
CC
UnitMin. Max. Min. Max. Min. Max.
V
Parameter Description Test Conditions Max. Unit
C
IN
C
OUT
Notes:
1. V
(min.) = –2.0 V fo r pulse durati ons of l ess tha n 20 ns .
IL
2. Tested initially and after any design or process changes that may affect these parameters.
Input Capacitance TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF
I/O Capacitance 8 pF
Document #: 38-05232 Rev. *B Page 3 of 11
CY7C1011CV33
AC Test Loads and Waveforms
10-ns devices:
OUTPUT
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
Z = 50
[3]
Ω
50Ω
30 pF*
1.5V
12-, 15-ns devices:
3.3V
OUTPUT
30 pF
(a)
R 317Ω
R2
351Ω
(b)
High-Z characteristics:
R 317Ω
3.0V
GND
Rise Time: 1 V/ns
ALL INPUT PULSES
90%
10%
(c)
90%
10%
Fall Time: 1 V/ns
AC Switching Characteristics Over the Operating Range
[4]
3.3V
OUTPUT
5 pF
R2
351Ω
(d)
-10 -12 -15
Parameter Description
UnitMin. Max. Min. Max. Min. Max.
Read Cycle
[5]
t
power
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
Write Cycle
t
WC
Notes:
3. AC characteristics (except High-Z) for all 10-ns parts are tested using the load conditions shown in (a). All other speeds are tested using the Thevenin load
shown in (b). High-Z characteristics are tested for all speeds using the test load shown in (d).
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
5. t
POWER
6. t
7. At any given temperature and voltage condition, t
8. The internal write time of the memory is defined by the overlap of CE
9. The minimum write cycle time for Write Cycle No. 3 (WE
, t
HZOE
signals can termina te the write. The i nput d ata se t-up an d hol d timing should be ref erenced to th e leadin g edge of th e signal that terminat es th e write.
VCC(typical) to the first access 1 1 1 µs
Read Cycle Time 10 12 15 ns
Address to Data Valid 10 12 15 ns
Data Hold from Address Change 3 3 3 ns
CE LOW to Data Valid 101215ns
OE LOW to Data Valid 5 6 7 ns
OE LOW to Low-Z 0 0 0 ns
[7]
[6, 7]
[6, 7]
567ns
333 ns
567ns
OE HIGH to High-Z
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power-up 0 0 0 ns
CE HIGH to Power-down 10 12 15 ns
Byte Enable to Data Valid 5 6 7 ns
Byte Enable to Low-Z 0 0 0 ns
Byte Disable to High-Z 6 6 7 ns
[8, 9]
Write Cycle Time 10 12 15 ns
gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed.
HZCE
, and t
are specified w ith a load c apac itance of 5 pF as in p art (d) of A C Test Loads. Transit ion is measur ed ± 500 mV from steady-stat e volt age.
HZWE
is less than t
HZCE
controlled, OE LOW) is the sum of t
, t
LZCE
is less than t
HZOE
LOW, an d WE LOW. CE and WE must be LOW to initi ate a write, and the transitio n of either of these
LZOE
, and t
HZWE
is less than t
HZWE
and tSD.
for any given device.
LZWE
Document #: 38-05232 Rev. *B Page 4 of 11
CY7C1011CV33
AC Switching Characteristics Over the Operating Range (continued)
-10 -12 -15
Parameter Description
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
CE LOW to Write End 7 8 10 ns
Address Set-up to Write End 7 8 10 ns
Address Hold from Write End 0 0 0 ns
Address Set-up to Write Start 0 0 0 ns
WE Pulse Width 7 8 10 ns
Data Set-up to Write End 5 6 7 ns
Data Hold from Write End 0 0 0 ns
WE HIGH to Low-Z
WE LOW to High-Z
[7]
[6, 7]
333 ns
567ns
Byte Enable to End of Write 7 8 10 ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
t
CDR
CE
VDR> 2V
[4]
UnitMin. Max. Min. Max. Min. Max.
3.0V3.0V
t
R
Switching Waveforms
Read Cycle No. 1
ADDRESS
DATA OUT
Notes:
10. Device is continuously selected. OE
is HIGH for read cycle.
11. WE
[10, 11]
PREVIOUS DATA VALID DATA VALID
t
OHA
, CE, BHE and/or BHE = VIL.
t
AA
t
RC
Document #: 38-05232 Rev. *B Page 5 of 11
CY7C1011CV33
Switching Waveforms (continued)
Read Cycle No. 2(OEControlled)
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH IMPEDANCE
t
LZCE
t
PU
Write Cycle No. 1 (CE Controlled)
ADDRESS
[11, 12]
t
ACE
t
DOE
t
LZOE
t
DBE
t
LZBE
[13, 14]
50%
t
RC
t
HZOE
t
HZCE
t
DATA VALID
HZBE
t
PD
HIGH
IMPEDANCE
I
ICC
CC
50%
I
ISB
SB
t
WC
t
CE
SA
WE
BHE, BLE
DATAI/O
Notes:
12. Address valid prior to or coincident with CE
13. Data I/O is high-impedance if OE
14. If CE
goes HIGH simultaneously wit h WE goin g HIGH, the outp ut remai ns in a hig h-impedanc e st ate.
or BHE and/or BLE = VIH.
transition LOW .
t
SCE
t
AW
t
PWE
t
BW
t
SD
t
HA
t
HD
Document #: 38-05232 Rev. *B Page 6 of 11
CY7C1011CV33
Switching Waveforms (continued)
Write Cycle No. 2 (BLE
ADDRESS
,BLE
BHE
WE
CE
DATAI/O
Write Cycle No.3
(WE
orBHE Controlled)
t
SA
Controlled,
t
WC
t
BW
t
AW
t
PWE
t
SCE
t
SD
t
HA
t
HD
ADDRESS
CE
WE
BHE
, BLE
DATA I/O
t
WC
t
SCE
t
AW
t
SA
t
BW
t
HZWE
t
PWE
t
SD
t
HA
t
HD
t
LZWE
Document #: 38-05232 Rev. *B Page 7 of 11
Truth Table
CY7C1011CV33
CE OE WE BLE BHE I/O0–I/O
H X X X X High-Z High-Z Power-down Standby (ISB)
L L H L L Data Out Data Out Read All Bits Active (ICC)
L L H L H Data Out High-Z Read Lower Bi ts Only Active (ICC)
L L H H L High-Z Data Out Read Upper Bits Only Active (ICC)
L X L L L Data In Data In Write All Bits Active (ICC)
L X L L H Data In High-Z Write Lower Bits Only Active (ICC)
L X L H L High-Z Data In Write Upper Bits Only Active (ICC)
L H H X X High-Z High-Z Sel ected, Outputs Disabled Active (ICC)
7
I/O8–I/O
15
Mode Power
Ordering Information
Speed
(ns) Ordering Code
10 CY7C1011CV33-10ZC Z44 44-pin TSOP II
CY7C1011CV33-10BVC BV48A 48-ball VFBGA
CY7C1011CV33-10ZI Z44 44-pin TSOP II
CY7C1011CV33-10BVI BV48A 48-ball VFBGA
12 CY7C1011CV33-12ZC Z44 44-pin TSOP II
CY7C1011CV33-12AC A44 44-pin TQFP
CY7C1011CV33-12BVC BV48A 48-ball VFBGA
CY7C1011CV33-12ZI Z44 44-pin TSOP II
CY7C1011CV33-12AI A44 44-pin TQFP
CY7C1011CV33-12BVI BV48A 48-ball VFBGA
15 CY7C1011CV33-15ZC Z44 44-pin TSOP II
CY7C1011CV33-15AC A44 44-pin TQFP
CY7C1011CV33-15BVC BV48A 48-ball VFBGA
CY7C1011CV33-15ZI Z44 44-pin TSOP II
CY7C1011CV33-15AI A44 44-pin TQFP
CY7C1011CV33-15BVI BV48A 48-ball VFBGA
Package
Name Package Type
Operating
Range
Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Document #: 38-05232 Rev. *B Page 8 of 11
Package Diagrams
CY7C1011CV33
44-Pin TSOP II Z44
44-Lead Thin Plastic Quad Flat Pack A44
51-85087-*A
51-85064-*B
Document #: 38-05232 Rev. *B Page 9 of 11
Package Diagrams (continued)
CY7C1011CV33
48-Lead VFBGA (6 x 8 x 1 mm) BV48A
51-85150-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05232 Rev. *B Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than cir cuitry embodi ed in a Cypress S emiconductor product . Nor does it convey or imply any license un der patent or other righ ts. Cypre ss Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1011CV33
Document History Page
Document Title: CY7C1011CV33 128K x 16 Static RAM
Document Number: 38-05232
REV. ECN NO.
** 117132 07/31/02 HGK New Data Sheet
*A 118057 08/19/02 HGK Pin configuration for 48-ball FBGA correction
*B 119702 10/11/02 DFP Updated FBGA to VFBGA; updated package code on page 8 to BV48A.
Issue
Date
Orig. of
Change Description of Change
Updated address pi nouts on p age 1 to A0 to A16. Updated C MOS st andby
current on page 1 from 8 to 10 mA.
Document #: 38-05232 Rev. *B Page 11 of 11
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