Cypress Semiconductor CY7C107-15VCT, CY7C107-15VC, CY7C1007-15VC, CY7C1007-12VCT, CY7C1007-12VC Datasheet

1M x 1 Static RAM

CY7C107

CY7C1007

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1992 – Revised September 3, 1999

Features

• High speed
—t

AA

= 12 ns

• CMOS for optimum speed/power

• Low active power
—825 mW

• Low standb y p ow er
—275 mW

• 2.0V data retention (opti onal)

—

100 µW

• Automat ic power-down when deselected

• TTL-compatibl e inputs and outputs

Functional Description

The CY7C107 and CY7C1007 are high-performance CMOS
static RAMs organized as 1,048,576 words by 1 bit. Easy

memory expansion is p rovi ded by an activ e LO W Chip Enabl e
(CE

) and three-state drivers. Thes e devices hav e an automatic
power-down feature that reduces po wer co nsumpt ion b y mor e
than 65% when deselected.

Writing to the devices is accomplished by taking Chip Enable
(CE

) and Write Enable ( WE) inputs LO W . Dat a on the inpu t pin
(D

IN

) is written into the memory location specified on the ad-

dress pins (A

0

through A19).

Reading from the devices is accomplished by taking Chip En­able (CE

) LOW while Write Enable ( WE) remains HIGH. Under
these conditions, the contents of the memory location speci­fied by t he address pi ns will appear on the data output (D

OUT

)

pin.
The output pin (D

OUT

) is placed in a high-impedance state

when the device is deselected (CE

HIGH) or during a write

operation (CE

and WE LOW).

The CY7C107 is av ailab le in a standard 40 0-mil-wi de SOJ; the
CY7C1007 is available in a standard 300-mil-wide SOJ.

LogicBlock Diagram Pin Configuration

Top View

SOJ

512x2048

ARRA

Y

A

5

A

6

A

7

COLUMN

DECODER

ROW DECODER

SENSE AMPS

POWER

DOWN

WE

CE

INPUT BUFFER

D

OUT

D

IN

A

4

A

3

A

2

A

1

A

0

1
2
3
4
5
6
7
8
9
10
11

14

15

16

20
19
18
17

21

24
23
22

12
13

25

28
27
26

GND

A

11

A

12

A

13

A

14

WE

V

CC

A

9

A

10

CE

A

0

D

OUT

D

IN

A

8

A

7

A

6

A

2

A

1

A

4

NC

NC

A

15

A

16

A

8

A12A14A16A

15

A10A11A

13

A17A18A

19

A

17

A

18

A

19

A

5

A

3

A

9

107-1

107-2

Selection Guid e

7C107-12

7C1007-12

7C107-15

7C1007-15

7C107-20

7C1007-20

7C107-25

7C1007-25

7C107-35

Maximum Access Time (ns) 12 15 20 25 35
Maximum Operating

Current (mA)

150 135 125 120 110

Maximum Standb y
Current (mA)

50 40 30 30 25

CY7C107

CY7C1007

2

Maximum Ratings

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +1 5 0 °C

Ambient Temperature with

Po wer Applied..................................................−55°C to +125°C

Supply Voltage on V

CC

Relative to GND

[1]

.....−0.5V to +7.0V

DC V oltage Applied to Outputs
in High Z State

[1]

....................................... −0.5V to V

CC

+ 0.5V

DC Input Voltage

[1]

....................................−0.5V to V

CC

+ 0.5V

Curre n t in to Out p ut s (L OW ).......... ............................... 20 mA

Static Discharge Voltage .......... ............ ............ .........>2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current .....................................................>200 mA

Notes:

1. V

IL

(min.) = –2.0V for pulse durations of less than 20 ns.

2. T

A

is the “instant on” case temperature.

3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.

Operating Range

Range

Ambient

Temperature

[2]

V

CC

Commercial 0°C to +70°C 5V ± 10%
Industrial

−40°C to +85 °C

5V ± 10%

Electrical Characteristics

Over the Operating Range

Parameter Description Test Conditions

7C107-12

7C1007-12

7C107-15

7C1007-15

7C107-20

7C1007-20

Min. Max. Min. Max. Min. Max. Unit

V

OH

Output HIGH
Voltage

VCC = Min., IOH = −4.0 mA 2.4 2.4 2.4 V

V

OL

Output LOW
Voltage

VCC = Min., IOL = 8.0 mA 0.4 0.4 0.4 V

V

IH

Input HIGH
Voltage

2.2 VCC+

0.3

2.2 VCC+

0.3

2.2 VCC+

0.3

V

V

IL

Input LOW
Voltage

[1]

−0.3 0.8 −0.3 0.8 −0.3 0.8 V

I

IX

Input Load Current GND < VI < V

CC

−1+1−1+1−1+1µA

I

OZ

Output Leakage
Current

GND < VI < VCC,
Output Disabled

–5+5–5+5–5+5µA

I

OS

Output Short
Circuit Current

[3]

VCC = Max., V

OUT

= GND −300 −300 −300 mA

I

CC

VCC Operating
Supply Current

VCC = Max.,
I

OUT

= 0 mA,

f = f

MAX

= 1/t

RC

150 135 125 mA

I

SB1

Automatic CE
Power-Down
Curr ent— TTL Inputs

Max. VCC, CE > VIH,
V

IN

>V

IH

or VIN < VIL,

f = f

MAX

50 40 30 mA

I

SB2

Automatic CE
Power-Down
Curr ent—
CMOS Inputs

Max. V

CC

,

CE

> VCC – 0.3V,

V

IN

> VCC – 0.3V or

V

IN

< 0.3V, f = 0

222mA

CY7C107

CY7C1007

3

Electrical Characteristics

Over the Operating Range (continued)

Parameter Description Test Conditions

7C107-25

7C1007-25 7C107-35

Min. Max. Min. Max. Unit

V

OH

Output HIGH
Voltage

VCC = Min., IOH = −4. 0 mA 2.4 2.4 V

V

OL

Output LO W Voltage VCC = Min., IOL = 8.0 mA 0.4 0.4 V

V

IH

Input HIGH Voltage 2.2 V

CC

+ 0.3 2.2 V

CC

+ 0.3 V

V

IL

Input LOW Voltage

[1]

−0.3 0.8 −0.3 0.8 V

I

IX

Input Load Current GND < VI < V

CC

−1+1−1+1µA

I

OZ

Output Leakage
Current

GND < VI < VCC,
Output Disabled

−5+5−5+5µA

I

OS

Output Short
Circuit Current

[3]

VCC = Max., V

OUT

= GND −300 −300 mA

I

CC

VCC Operating
Supply Current

VCC = Max.,
I

OUT

= 0 mA,

f = f

MAX

= 1/t

RC

120 110 mA

I

SB1

Autom atic CE
Power-Down
Current—TTL Inputs

Max. VCC, CE > VIH,
V

IN

>VIH or VIN < VIL,

f = f

MAX

30 25 mA

I

SB2

Autom atic CE
Power-Down
Current—CMOS Inputs

Max. V

CC

,

CE

> VCC – 0.3V,

V

IN

> VCC – 0.3V or

V

IN

< 0.3V , f = 0

22mA

Capacitance

[4]

Parameter Description Test Conditions Max. Unit

C

IN

: A ddre sses Input Capacitance TA = 25°C, f = 1 MHz,

V

CC

= 5.0V

7pF

C

IN

: Controls 10 pF

C

OUT

Output Capacitance 10 pF

Note:

4. Tested initially and after any design or process changes that may affect these parameters.

CY7C107

CY7C1007

4

AC Test Loads and Waveforms

3.0V

5V

OUTPUT

R1 480

Ω

R2

255

Ω

30pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

≤

3

ns

≤

3

ns

5V

OUTPUT

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT 1.73V

Equivalentto: THÉ VENIN EQUIVALENT

ALL INPUT PULSES

R2

255

Ω

R1 480

Ω

167

Ω

107-3

107-4

Switching Characteristics

[5]

Over the Operating Range

7C107-12

7C1007-12

7C107-15

7C1007-15

7C107-20

7C1007-20

7C107-25

7C1007-25 7C107-35

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC

Read Cycle Time 12 15 20 25 35 ns

t

AA

Address to Data Valid 1215202535ns

t

OHA

Data Hold from Address
Change

33333ns

t

ACE

CE LOW to Data Valid 1215202535ns

t

LZCE

CE LOW to Low Z

[6]

33333ns

t

HZCE

CE HIGH to High Z

[6, 7]

6781010ns

t

PU

CE LOW to Power-Up 0 0 0 0 0 ns

t

PD

CE HIGH to Power-Down 12 15 20 25 35 ns

WRITE CYCLE

[8]

t

WC

Write Cycle Time 12 15 20 25 35 ns

t

SCE

CE LOW to Write End1012152025 ns

t

AW

Address Set-Up to Write
End

10 12 15 20 25 ns

t

HA

Address Hold from Write
End

00000ns

t

SA

Address Set-Up to Write
Start

00000ns

t

PWE

WE Pulse Width 1012 152025 ns

t

SD

Data Set-Up to Write End 7 8 10 15 20 ns

t

HD

Data Hold from Write End 0 0 0 0 0 ns

t

LZWE

WE HIGH to Low Z

[6]

33333ns

t

HZWE

WE LOW to Hig h Z

[6, 7]

6781010ns

Notes:

5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I

OL/IOH

and 30-pF load cap acitance.

6. At any given temperature and voltage condition, t

HZCE

is less than t

LZCE

and t

HZWE

is less tha n t

LZWE

for any given de vice .

7. t

HZCE

and t

HZWE

are specified with a load capa citan ce of 5 pF a s in part (b) of A C Test Loads. Transition is measured ±500 mV from stea dy-state vol tag e.

8. The internal write time of the memory is defined by the overlap of CE

LOW and WE LOW . CE a nd WE must be LO W to initia te a write, and the transi tion of any of these

signals can terminate the write . The i nput data set-up and ho ld timing s hould be ref er enced to the leadi ng edge o f the signal that terminates the writ e.

CY7C107

CY7C1007

5

Data Rete n ti o n C h ar acteristics

Over the Operating Range (L Version Only)

Parameter Description Conditions

[9]

Min. Max. Unit

V

DR

VCC for Data Retention 2.0 V

I

CCDR

Data Retention Curren t VCC = VDR = 2.0V,

CE

> VCC – 0.3V,

V

IN

> VCC – 0.3 or

V

IN

< 0.3V

50

µA

t

CDR

[4]

Chip Deselect to Data Retention Ti me 0 ns

t

R

[4]

Operation Recovery Time t

RC

ns

Data Retention Waveform

4.5V4.5V

CE

V

CC

t

CDR

VDR> 2V

DATA RETENTION MODE

t

R

107-5

Switching Waveforms

Read Cycle No. 1

[10, 11]

Read Cycle No. 2

[11, 12]

Notes:

9. No input may exceed V

CC

+ 0.5V.

10. Device is continuously selected, CE

= VIL.

11. WE

is HIGH for read cycle.

12. Address valid prior to or coincident with CE trans ition LO W.

PREVIOUS DATA VALID DATA VALID

t

RC

t

AA

t

OHA

107-6

ADDRESS

DATA OUT

50%

50%

DATA VALID

t

RC

t

ACE

t

LZCE

t

PU

HIGH IMPEDANCE

t

HZCE

t

PD

HIGH

ICC
ISB

IMPEDANCE

ADDRESS

CE

DA TA OUT

V

CC

SUPPLY

CURRENT

107-7

CY7C107

CY7C1007

6

Write Cycle No. 1 (CE Contr oll ed)

[13]

Write Cycle No. 2 (WE Controlled)

[13]

Note:

13. If CE

goes HIGH simu ltaneousl y with WE g oing HI GH, the output remain s in a hi gh-impedanc e state.

Switching Waveforms

(continued )

DATA VALID

t

SCE

t

AW

t

SA

t

PWE

t

HA

t

HD

t

SD

t

WC

HIGH IMPEDANCE

ADDRESS

CE

WE

DA TA OUT

DATA IN

107-8

t

WC

DATA VALID

DATA UNDEFINED

HIGH IMPEDANCE

t

SCE

t

AW

t

SA

t

PWE

t

HA

t

HD

t

HZWE

t

LZWE

t

SD

ADDRESS

CE

WE

DATA OUT

DATA IN

107-9

CY7C107

CY7C1007

7

Truth Table

CE WE D

OUT

Mode Power

H X High Z Power-Down Standby (ISB)

L H Data Out Read Active (ICC)
L L High Z Write Active (ICC)

Ordering Information

Speed

(ns) Or deri ng Code

Package

Name Package Type

Operating

Range

12 CY7C107-12VC V28 28-Lead (400-Mil) Molded SOJ Commercial

CY7C1007-12VC V21 28-Lead (300-Mil) Molded SOJ

15 CY7C107-15VC V28 28-Lead (400-Mil) Molded SOJ Commercial

CY7C1007-15VC V21 28-Lead (300-Mil) Molded SOJ

15 CY7C107-15VI V28 28-Lead (400-Mil) Molded SOJ Industrial

CY7C1007-15VI V21 28-Lead (300-Mil) Molded SOJ

20 CY7C107-20VC V28 28-Lead (400-Mil) Molded SOJ Commercial

CY7C1007-20VC V21 28-Lead (300-Mil) Molded SOJ

25 CY7C107-25VC V28 28-Lead (400-Mil) Molded SOJ Commercial

CY7C1007-25VC V21 28-Lead (300-Mil) Molded SOJ

Contact factory for “L” version availability.

Document #: 38-00232-C

Package Diagrams

28-Lead (300-Mil) Molded SOJ V21

51-85031-B

CY7C107

CY7C1007

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagrams

(continued)

28-Lead (400-Mil) Molded SOJ V28

51-85032-A