Cypress Semiconductor CY7C006-25JI, CY7C006-25JC, CY7C006-25AC, CY7C006-15JC, CY7C006-15AC Datasheet

with Sem, Int, Busy

Features

• True dual-ported memory cells which allow
simultaneous reads of the same memory location

• 16K x 8 organizat ion (CY7C006)

• 16K x 9 organizat ion (CY7C016)

• 0.65-micron CMOS for optim um speed/power

• High-speed access: 15 ns

• Low op e rating pow er: I

= 140 mA (typ.)

CC

• Fully asy nchronous operation

• Automatic power-down

• TTL compatible

• Expandab le dat a bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device

• Busy arbitration scheme provided

• Semaphores i ncluded to per mit software hand shaking
between ports

flag for port-to-port communication

•INT

• Available in 68-pin PLCC (7C006), 64-pin (7C006) and
80-pin (7 C016) TQFP

• Pin compatible and functional equivalent to
IDT7006/IDT7016

Functional Description

The CY7C006 and CY7C016 are high-speed CMOS 16K x 8
and 16K x 9 dual-port static RAMs. Various arbitration

CY7C006
CY7C016

16K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

schemes are included on the CY7C006/016 to handle situa­tions when mul tiple processors access t he same pi ece of d ata.
Two ports are provided, permitting independent, asynchro­nous access for reads and writes to any location in memory.
The CY7C006/016 can be utilized as a standalone
128-/144-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16-/18-bit or wider mas­ter/slave dual-port static RAM. An M/S
plementing 16-/18-bit or wider memory applications without
the need for separate master and slave devices or additional
discrete logic. Application areas include interprocessor/multi­processor designs, communications status buffering, and du­al-port video/grap hics memory.

Each port has independent control pins: Chip Enable (CE
Read or Write Enable (R/W
flags, BUSY

and INT, are provided on each port. BUSY signals

), and Output Enable (OE). Two

that the port is trying to access the same location currently
being accessed by t he other port. The Int errupt fla g (INT
mits communication between ports or systems b y means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indica te that a shared r esource i s
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re­source is in use. An automatic power-down feature is con­trolled independently on each port by a Chip Enable (CE
or SEM

pin.

The CY7C006 and CY7C016 are available in 68-pin PLCC
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.

pin is provided for im-

),

) per-

) pin

R/W

CE
OE

I/O

I/O

BUSY

A

A

13L

L

L
L

8L
7L

0L

[1,2]

L

0L

SEM

L

[2]

INT

L

Logic Block Diagram

(7C016)I/O

Notes:

1. BUSY

2. Interrupt: push-pull output and requires no pull-up resistor.

is an output in master mode and an input in slave mode.

ADDRESS

DECODER

CE
OE

R/W

I/O

CONTROL

L

L
L

MEMORY

ARRAY

INTERRUPT

SEMAPHORE

ARBITRATION

M/S

I/O

CONTROL

ADDRESS
DECODER

CE

R

OE

R

R/W

R

SEM
INT

R
[2]

R

R/W

R

CE

R

OE

R

I/O8R(7C016)
I/O

7R

I/O

0R

[1,2]

BUSY

R

A

13R

A

0R

C006-1

Cypress Semiconductor Corporation

• 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 22, 1999

Pin Configurations

I/O
I/O
I/O
I/O

GND
I/O
I/O

V

GND

I/O
I/O
I/O

V

I/O
I/O
I/O
I/O6

CY7C006
CY7C016

68-Pin PLCC

Top View

)

[3]

8L

L

L

0L

OE

I/O1LI/O

NC(I/O

987654321

10

2L

11

3L
4L

12

5L

13
14

6L

15

7L

16
17

CC

18

0R

19

1R

20

2R

21

CC

22

23

3R

24

4R
5R

25

R

26

2930313233683467356636653764386339

)

R

7R

[3]

OE

8R

I/O

R

R/W

R

R

CE

SEM

CELSEMLR/W

CY7C006

NC

NC(I/O

NC

A

13R

13L

A

GND

CC

V

12RA11RA10R

A

12LA11LA10LA9LA8LA7LA6L

A

62

40

4127422843

6R

A9RA8RA7RA

61

60

A

5L

59

A

4L

58

A

3L

57

A

2L

56

A

1L

55

A

0L

54

INT

L

BUSY

53
52
51
50
49

48
47
46
45
44

5R

A

GND
M/S
BUSY

INT

A

0R

A

1R

A

2R

A

3R

A

4R

L

R

R

C006-2

Note:

3. I/O for CY7C016 only.

I/O
I/O

I/O
I/O
GND
I/O
I/O

V

GND
I/O
I/O
I/O

V
I/O
I/O
I/O

64-Pin TQFP

Top View

L

L

L

0L

OE

I/O1LI/O

R/W

2L
3L

4L
5L

1
2
3
4

13L

CC

V

A

CELSEM

12LA11LA10LA9LA8LA7LA6L

A

5

6L
7L

CC

6
7
8

CY7C006

9

0R
1R
2R

CC

3R
4R
5R

10
11
12
13
14

15
16

17641863196220612160225923582457255626552754285329523051315032

R

R

R

R

6R

7R

OE

I/O

I/O

R/W

SEM

CE

A

13R

A

GND

12RA11RA10R

A9RA8RA7RA

5L

A

49

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

5R

6R

A

A

4L

A

3L

A

2L

A

1L

A

0L

INT
BUSY
GND
M/S

BUSY
INT
A

0R

A

1R

A

2R

A

3R

A

4R

L

L

R

R

C006-3

2

CY7C006
CY7C016

Pin Configurations

(continued)

NC

I/O

2L

I/O

3L

I/O

4L

I/O

5L

GND

I/O

6L

I/O

7L

V

CC

NC

GND

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

NC

80-Pin TQFP

Top View

L

L

8L

1L

OE

I/O0LI/O

I/O

8079787776757473727170696867666465

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

16
17
18
19
20

2122232425262728293031323334353736

R

R

R

R

7R

I/O

I/O

8R

OE

R/W

SEM

CE

NC

CELSEMLR/W

NCANC

13L

A

NC

CY7C016

13R

GND

12LA11LA10LA9LA8LA7LA6L

CC

V

A

12RA11RA10R

A

A9RA8RA7RA

6R

NC

636261

383940

5R

NC

A

NC

NC

NC

60

A

5L

59

A

4L

58

A

3L

57

A

2L

56

A

1L

55

A

0L

54

INT
BUSY
GND
M/S

BUSY
INT

A

0R

A

1R

A

2R

A

3R

A

4R

NC
NC

C006-4

L

L

R

R

53
52

51
50
49
48
47
46

45
44
43
42
41

Pin Definitions

Left Port Right Port Description

I/O

0L–7L(8L)

A

0L–13L

CE

L

OE

L

R/W

L

SEML SEM

INT

L

BUSY

L

M/S Master or Slave Select
V

CC

GND Ground

I/O

0R–7R(8R)

A

0R–13R

CE

R

OE

R

R/W

INT

R

BUSY

Data Bus Input/Output
Address Lines
Chi p E nable
Output Enable

R

R

Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-

phores. The three least significant bits of the address lines will dete rmine
which semaphore to write or read. The I/O
semaphore. Semaph ores are requested by writi ng a 0 into the respective
location.

Interrupt Flag. INTL is set when right port writes location 3FFE and is
cleared when left port reads loc ation 3FFE. I NT
location 3FFF and is clear ed when right port reads location 3FFF.

R

Busy Flag

Power

pin is used when writing to a

0

is set when left port writes

R

3

CY7C006
CY7C016

Selection G uide

7C006-15
7C016-15

Maximum Access Time (ns) 15 25 35 55
Maximum Operating

260 220 210 200

Current (mA)
Maximum Standby

Current for I

SB1

(mA)

70 60 50 40

7C006-25
7C016-25

7C006-35
7C016-35

7C006-55
7C016-55

Maximum Ratings

(Abov e which the useful lif e m ay be impaired. For user guide­lines, not tested.)

Storage Temperature .............. ...................–65°C to +1 5 0°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage to Ground Potential...............–0.5V to +7.0V

DC Voltage Applied to Outputs

in High Z State............................................... –0.5V to +7.0V

[4]

DC Input Voltage

Electrical Characteristics

......................................... –0.5V to +7.0V

Over the Operating Range

Output Current into Outputs (LOW)............................. 20 mA

Static Discharge Voltage ......................... .. ............... >2001V

(per MIL-STD-883, Method 3015)

Latch-Up Current............. ............ ............ ............ ... >200 mA

Operating Range

Range

Commercial 0°C to +70°C 5V ± 10%
Industrial –40°C to +85°C 5V ± 10%

7C006-15
7C016-15

Ambient

Temperature V

7C006-25
7C016-25

CC

Parameter Description T est Conditions Min. Typ. Max. Min. Typ. Max. Unit

V

OH

V

OL

V

IH

V

IL

I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

Notes:

4. Pulse width < 20 ns.

5. f

MAX

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND ≤ VI ≤ V

CC

Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V
Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(One Port CMOS Level)

= 1/tRC = All inputs c ycling at f = 1/tRC (except output enab le) . f = 0 mea ns no add ress or contr ol lines change . T his appl ies onl y to inpu ts at C MOS le v el s tandby I

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

MAX

MAX

[5]

[5]

Both Ports
CE

and CER ≥ VCC – 0.2V,

V

≥ VCC – 0.2V

IN

or V

≤ 0.2V, f = 0

IN

One Port
CE

or CER ≥ VCC – 0.2V,

L

V

≥ VCC – 0.2V or

IN

V

≥ 0. 2V, Active

IN

Port Outputs, f = f

OUT

= 0 mA

[5]

[5]

MAX

Com’l 170 260 160 220 mA
Ind 160 270
Com’l 50 70 40 60 mA
Ind 40 75
Com’l 110 170 90 130 mA
Ind 90 150
Com’l 3 15 3 15 mA
Ind 3 15

Com’l 100 150 80 120 mA
Ind 80 130

–10 +10 –10 +10
–10 +10 –10 +10

CC

µA
µA

SB3

.

4

CY7C006
CY7C016

Electrical Characteristics

(continued)

7C006-35
7C016-35

7C006-55
7C016-55

Parameter Description T est Conditions Min. Typ. Max. Min. Typ. Max. Unit

V
V
V
V
I

IX

I

OZ

I

CC

I

SB1

I

SB2

I

SB3

I

SB4

OH
OL
IH
IL

Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 2.4 V
Output LOW Voltage VCC = Min., IOL = 4.0 mA 0.4 0.4 V

2.2 2.2 V
Input LOW Voltage 0.8 0.8 V
Input Leakage Current GND ≤ VI ≤ V

CC

Output Leakage Current Outputs Disabled, GND ≤ VO ≤ V
Operating Current VCC = Max., I

Outputs Disabled

Standby Current
(Both Ports TTL Levels)

Standby Current
(One Port TTL Level)

Standby Current
(Both Ports CMOS
Levels)

Standby Current
(One Port CMOS Level)

CEL and CER ≥ VIH,
f = f

CEL or CER ≥ VIH,
f = f

MAX

MAX

[5]

[5]

Both Ports
CE

and CER ≥ VCC – 0.2V,

V

≥ VCC – 0.2V

IN

or V

≤ 0.2V, f = 0

IN

One Port
CE

or CER ≥ VCC – 0.2V,

L

V

≥ VCC – 0.2V or

IN

V

≤ 0. 2V, Active

IN

Port Outputs, f = f

OUT

= 0 mA

[5]

[5]

MAX

Com’l 150 210 140 200 mA
Ind 150 250 140 240
Com’l 30 50 20 40 mA
Ind 30 65 20 55
Com’l 80 120 70 100 mA
Ind 80 130 70 115
Com’l 3 15 3 15 mA
Ind 3 15 3 15

Com’l 70 100 60 90 mA
Ind 70 110 60 95

–10 +10 –10 +10
–10 +10 –10 +10

CC

µA
µA

Capacitance

[6]

Parameter Description Test Conditions Max. Unit

C

IN

C

OUT

Input Capacitance TA = 25°C, f = 1 MHz,

V

= 5.0V

Output Capacitance 10 pF

CC

AC Test Loads and Waveforms

5V

R1=893

R2=347

C006-5

C006-8

Ω

Ω

OUTPUT

C= 30

pF

(a) Normal Load (Load 1)

OUTPUT

C = 30 pF

Load (Load 2)

Note:

6. Tested initially and after any design or process changes that may affect these parameters.

3.0V

GND

OUTPUT

C=30 pF

(b) ThéveninEquivalent (Load)

ALL INPUT PULSES

90%

≤

10%

3ns

=250

R

TH

10 pF

5V

R1=893

R2=347

Ω

Ω

Ω

=1.4V

V

TH

90%

10%

≤

OUTPUT

C= 5pF

C006-6 C006-7

ns

3

C006-9

(c) Three-State Delay (Load 3)

5

CY7C006
CY7C016

Switching Characteristics

Over the Operating Range

[7]

7C006-15
7C016-15

7C006-25
7C016-25

7C006-35
7C016-35

7C006-55
7C016-55

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

READ CYCLE

t

RC

t

AA

t

OHA

t

ACE

t

DOE

t

LZOE

t

HZOE

t

LZCE

t

HZCE

t

PU

t

PD

[8, 9, 10]

[8, 9, 10]

[8, 9, 10]

[8, 9, 10]
[10]
[10]

Read Cycle Time 15 25 35 55 ns
Address to Data Valid 15 25 35 55 ns
Output Hold From Address Change 3 3 3 3 ns
CE LOW to Data Valid 15 25 35 55 ns
OE LOW to Data Valid 10 13 20 25 ns
OE Low to Low Z 3 3 3 3 ns
OE HIGH to High Z 10 15 15 25 ns
CE LOW to Low Z 3 3 3 3 ns
CE HIGH to High Z 10 15 15 25 ns
CE LOW to Po wer-Up 0 0 0 0 ns
CE HIGH to Power-Do wn 15 25 35 55 ns

WRITE CYCLE

t

WC

t

SCE

t

AW

t

HA

t

SA

t

PWE

t

SD

[11]

t

HD

[9, 10]

t

HZWE

[9, 10]

t

LZWE

[12]

t

WDD

[12]

t

DDD

BUSY TIMING

t

BLA

t

BHA

t

BLC

t

BHC

t

PS

t

WB

t

WH

[14]

t

BDD

Notes:

7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input pulse levels of 0 to 3.0V, and output loading of the specified
I

OI/IOH

8. At any given temperature and voltage condition for any given device, t

9. Test conditions used are Load 3.

10. This parameter is guaranteed but not tested.

11. Must be met by the device writing to the RAM under all operating conditions.

12. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.

13. Test conditions used are Load 2.

14. t

BDD

Write Cycle Time 15 25 35 55 ns
CE LOW to Write End 12 20 30 45 ns
Address Set-Up to Write End 12 20 30 45 ns
Address Hold From Write End 0 0 0 0 ns
Address Set-Up to Write Start 0 0 0 0 ns
Write Pulse Width 12 20 25 40 ns
Data Set-Up to Write End 10 15 15 25 ns
Data Hold Fro m Write End 0 0 0 0 ns
R/W LO W to High Z 10 15 20 25 ns
R/W HIGH to Low Z 3 3 3 3 ns
Write Pulse to Data Delay 30 50 60 80 ns
Write Da ta V a lid to Re a d Data Valid 25 30 35 60 ns

[13]

BUSY LOW from Address Match 15 20 20 30 ns
BUSY HIGH from Address Mismatc h 15 20 20 30 ns
BUSY LOW from CE LOW 15 20 20 30 ns
BUSY HIGH from CE HIGH 15 17 25 30 ns
Port Set-Up for Priority 5 5 5 5 ns
R/W LO W after BUSY LOW 0 0 0 0 ns
R/W HIGH after BUSY HIGH 13 17 25 30 ns
BUSY HIGH to Data Valid Note 13 Note 13 Note 13 Note 13 ns

and 30-pF load c apacitanc e.

is a calculated pa rameter and is the gr eat er of t

WDD

– t

(actual) or t

PWE

is less than t

HZCE

– tSD (actual).

DDD

LZCE

and t

HZOE

is less than t

LZOE

.

6

CY7C006
CY7C016

Switching Characteristics

Over the Operating Range

[7]

(continued)

7C006-15
7C016-15

7C006-25
7C016-25

7C006-35
7C016-35

7C006-55
7C016-55

Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit

INTERRUPT TIMING

t
t

INS
INR

INT Set Time 15 25 25 30 ns
INT Reset Time 15 25 25 30 ns

[13]

SEMAPHORE TIMING

t

SOP

t

SWRD

t

SPS

SEM Flag Update Pulse (OE or SEM) 10 10 15 20 ns
SEM Flag Write to Read Time 5 5 5 5 ns
SEM Flag Contention Window 5 5 5 5 ns

Switching Waveforms

Read Cycle No. 1 (Eith er Port Address Access)

ADDRESS

t

OHA

DATA OUT

[15, 16]

t

RC

t

AA

DATA VALI DPREVIOUS DATA VALID

C006-10

t

ACE

[15, 17, 18 ]

t

DOE

DATA VALI D

Read Cycle No. 2 (Either Port CE/OE Acce ss)

or CE

SEM

OE

t

LZOE

t

LZCE

DATA OUT

t

I

CC

I

SB

Notes:

15. R/W

is HIGH for read cycle.

16. Device is continuously selected CE = LO W a nd OE = LO W. This w av ef orm cann ot be used f or semaphor e reads .

17. Address valid prior to or coincident with CE

18. CEL = L, SEM = H when access ing RAM. CE = H, SEM = L whe n accessing sema phores .

PU

transition LOW .

t

HZOE

t

HZCE

t

PD

C006-11

7

CY7C006
CY7C016

Switching Waveforms

Read Timing with Port-to-Port Delay (M/S=L)

ADDRESS

DATA IN

ADDRESS

DAT A

R/W

OUTL

R

R

R

L

(continued )

[19, 20]

MATCH

MATCH

Write Cycle No. 1: OE Three- Sta te Data I/O s (E ither Port )

ADDRESS

t

SEMOR CE

R/W

SCE

t

AW

t

WC

[21, 22, 23]

t

WC

t

PWE

t

PWE

t

WDD

t

SD

VALID

t

DDD

t

HD

VALID

C006-12

t

HA

DATA I N

t

SA

t

SD

DATA VALID

t

HD

OE

t

HZOE

DA TA OUT

Notes:

19. BUSY

20. CEL = CER = LOW.

21. The internal write time of the memory is defined by the overlap of CE

22. If OE is LO W during a R/W controlled write cy cle, the write pulse widt h must be the larger of t

23. R/W

= HIGH for the writing port.

terminate a write by going HIGH. The data i np ut set- up and hold timi ng sh ould be r ef erenced t o the rising edge of the signal that terminates t he writ e.
the bus for the required t

specified t

.

PWE

must be HIGH dur ing all addres s trans itions .

. If OE is HIGH during a R/W controll ed write cycle (as in this example), this requirement does not apply and the w rite pulse can be as short as the

SD

HIGH IMPEDANCE

or SEM LOW and R/W LOW . Both s ignals must be LO W to initiate a wr ite, and either signal can

or (t

PWE

+ tSD) to allow the I/O driver s to turn off and data to be placed on

HZWE

t

LZOE

C006-13

8

CY7C006
CY7C016

Switching Waveforms

(continued )

Write Cycle No. 2: R/W Three- State Data I/Os (Either P ort)

t

ADDRESS

t

SCE

ORCE

SEM

t

[25]

AW

t

HZWE

t

R/W

SA

DATA I N

OUT

DAT A

Semaphore Read After Write Timing, Either Side

A0–A

2

VALID ADDRESS VALID ADDRESS

[20, 22, 24 ]

WC

t

PWE

t

SD

DA TA VALID

HIGH IMPEDANCE

t

AA

t

HA

t

HD

t

LZWE

C006-14

t

OHA

t

AW

t

SEM

I/O

t

SCE

0

t

SA

t

PWE

HA

t

SD

DA TAINVALID

t

HD

R/W

OE

WRITE CYCLE READ CYCLE

Notes:

24. Data I/O pins enter high-impedance when OE

25. CE = HIGH for the dur ation of the abo ve t iming (both wr ite and read c ycle).

is held LOW during w rite.

t

SWRD

t

SOP

t

SOP

t

ACE

t

DOE

DA TA

OUT

VALID

C006-15

9

CY7C006
CY7C016

Switching Waveforms

Semaphore Contention

A0L–A

2L

R/W

L

SEM

L

A0R–A

2R

R/W

R

SEM

R

(continued )

[26, 27, 28]

Read with BUSY (M/S=HIGH)

ADDRESS

R

[19]

MATCH

t

SPS

MATCH

t

WC

MATCH

C006-16

R/W

R

DATA IN

ADDRESS

DAT A

BUSY

OUTL

R

t

PS

L

L

Write Timing with Busy Input (M/S=LOW)

R/W

BUSY

t

WB

t

BLA

MATCH

t

PWE

t

PWE

t

WH

t

SD

VALID

t

WDD

t

DDD

t

HD

t

BHA

t

BDD

VALID

C006-17

Notes:

26. I/O

27. Semaphores are reset (available to both ports) at cycle start.

28. If t

= I/O0L = LOW (reques t semaph ore); CER = CEL = HIGH.

0R

is violated, the s emaphore w ill de fini tely be obt ai ned b y one si de or the ot her , b ut ther e is no gua ra ntee w hich s ide will control the semaphore.

SPS

C006-18

10

CY7C006
CY7C016

Switching Waveforms

(continued )

Busy Timing Diagram No. 1 (CE
CELVali d Fi rs t:

ADDRESS

CE

R

ADDRESS

L,R

CE

L

CE

R

BUSY

R

Valid First:

L,R

CE

R

CE

L

BUSY

L

Arbitration)

t

PS

t

PS

[29]

ADDRESS MATCH

t

ADDRESS MATCH

t

BLC

BLC

t

BHC

t

BHC

C006-19

C006-20

Busy Timing Diagram No. 2 (Address Arbitration)

Left AddressValid First:

or t

t

RC

WC

ADDRESS

ADDRESS

BUSY

L

R

R

ADDRESS MATCH

t

PS

t

BLA

Right Address Valid First:

tRCor t

WC

ADDRESS

ADDRESS

Notes:

29. If t

30. t

HA

31. t

INS

R

L

BUSY

L

is violated, the bus y s ignal will be asserted on one side or the other, but t here i s no guara ntee on whic h si de BU SY will be asserted.

PS

depends on which enab le pin ( CEL or R/WL) is deasserted first.

or t

depends on which ena ble p in (C EL or R/WL) is asserted last.

INR

ADDRESS MATCH ADDRESS MISMATCH

t

PS

t

BLA

[28]

ADDRESS MISMATCH

t

BHA

t

BHA

C006-21

C006-22

11

CY7C006
CY7C016

Switching Waveforms

Interrupt Timing Diagrams

Left Sid e Sets IN T

ADDRESS

CE

R/W

INT

L

L

L

R

Right Side Clears INTR:

ADDRESS

CE

R/W

OE

R

R

R

R

:

R

(continued )

WRITE 3FFF

31]

[

t

INS

t

WC

t

INR

[30]

t

HA

C006-23

t

RC

READ 3FFF

INT

R

Right Side Sets INTL:

ADDRESS

CE

R/W

INT

R

R

R

L

Left Side Clears INTL:

ADDRESS

CE

R/W

OE

R

L

L

L

WRITE 3FFF

[30]

t

INS

t

WC

t

INR

C006-24

[30]

t

HA

C006-25

t

RC

READ 3FFF

INT

L

C006-26

12

CY7C006
CY7C016

Architecture

The CY7C006/016 consists of a an array of 16K words of 8/9
bits each of dual-port RAM cells, I/O and address lines, and
control signals (CE
dent access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY
vided on each por t. Two Interrupt (INT
port-to-port communication. Two Semaphore (SEM
used for allocating shared resources. With the M/S
CY7C006/016 can function as a Master (BUSY
as a slave (BUSY
matic power-down feature controlled by CE
with its own Output Enable control (OE
from the device.

, OE, R/W). These control pins permit indepen-

pin is pro-

) pins can be utilized for

) control pins are

pin, the

pins are outputs) or

pins are inputs). The CY7C006/016 has an auto-

. Each port is provided

), which allows data to be read

Interrupts

The interrupt flag (INT

) permits communications between p orts.
When the left port writes to location 3FFF(HEX), the right port’s i nter­rupt flag (INT
that same location. Setting the left por t’s interrupt flag (INT

) is set. This flag is cleared when the right port reads

R

L

complished when the right p ort writes to locat ion 3FFE(HEX). This
flag is cleared when the left port reads location 3FFE(HEX). The mes­sage at 3FFE(HEX) and 3FFF(HEX) is user-defined. See Table 2 for
input requirements for INT

. INTR and INTL are push-pull outputs and

do not require pull-up resistors to operate.

Busy

The CY7C006/016 provides on-chip arbitration to resolve si­multaneous memory location access (contention). If both
ports’ CE

s are asserted and an address match occurs within tPS of

each other the Busy logic will determine which port has access. If t

Functional Description

Write Operation

Data must be set up for a duration of t
of R/W

in order to guarantee a valid write. A write operation is con­trolled by either the OE
R/W

pin (see Write Cycle No. 2 waveform). Data can be written to the
device t
edge of R/W

after the OE is deasserted or t

HZOE

. Required inputs for non-contention operations are sum-

pin (see Write Cycle No.1 waveform) or the

marized in T able 1 .
If a location is being written to by one port and the opposite

port attempts to read that location, a port-to-port flowthrough
delay must be met before the data is read on the output; oth­erwise the data read i s not deterministic. Data will be valid on
the port t

after the data is presented on the other port.

DDD

Table 1. Non-Contending Read/Write

Inputs Outputs

CE R/W OE SEM I/O

0–7/8

H X X H High Z Power-Down
H H L L Data Out Read Data in

X X H X High Z I/O Lines Disab led
H X L Data In Write to Semaphore

L H L H Data Out Read
L L X H Data In Write
L X X L Illega l C ondition

Read Operation

When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted. If the user of the CY7C006/016 wishes to access a sema­phore flag, then the SEM

pin must be asserted instead of the CE pin.

ACE

before the rising edge

SD

afte r the fa ll in g

HZWE

Operation

Semaphore

after CE or t

DOE

after OE are

is violated, one port will definitely gain permission to the location, but
it is not guaranteed which one. BUSY
address match or t
in master mode are push-pull outputs and do not require pull-up re-

after CE is taken LOW . BUSYL and BUSY

BLC

will be asserted t

BLA

after an

sistors to operate.

Master/Slave

An M/S

pin is provided in order to expand the word width by config­uring the device as either a master or a slave. The BUSY
the master is connected to the BUSY

input of the slave. This will allow

output of

the device to interface to a master device with no external compo­nents. Writing of slave devices must be delayed until after the BUSY
input has settled (t
cycle during a con ten tion situati on. W hen pr esented a HIGH input,
the M/S

pin allows the device to be used as a master and therefore

the BUSY

line is an o utput. BUSY can then be used to send the

). Otherwise, the slave chip may begin a write

BLA

arbitration outcome to a slave.

Semaphore Operation

The CY7C006/016 provides eight semaphore latches which
are separate from the dual-port memory locations. Sema­phores are used to reserve resources tha t are shared between
the two ports.The state of the semaphore indicates that a re­source is in use. For example, if the left port wants to request
a given resource, it sets a latch by writing a 0 to a semaphore
location. The left port then verifies its success in setting the
latch by reading it. After writing to the semaphore, SEM
must be deasserted for t
phore. The semaphore value will be available t
rising edge of the sem aphore write. If the left por t was successful

before attempting to read the sema-

SOP

SWRD

+ t

DOE

after the

(reads a 0), it assumes control over the shared resource, otherwise
(reads a 1) it assumes the right port has control and continues to poll
the semaphore.When the ri ght side has relinquished co ntrol of the
semaphore (by writing a 1), the left side will succeed in gaining control
of the semaphore. If the left side no longer requires the semaphore,
a 1 is written to cancel its request.

T able 2. Interrupt Operati on Exam ple (assumes BUSYL=BUSYR=HIGH)

Left Port Right Port

Function R/W CE OE A

0L–13L

INT R/W CE OE A

0R–13R

Set Left INT X X X X L L L X 3FFE X
Rese t Left INT X L L 3FFE H X L L X X
Set Right INT L L X 3FFF X X X X X L
Reset Right INT X X X X X X L L 3FFF H

) is ac -

PS

R

or OE

INT

13

CY7C006
CY7C016

Semaphores are accessed by asserting SEM
pin functions as a chip enable for the semaphore latches (CE must
remain HIGH during SEM
address. OE
memory access.When writing or reading a semaphore, the other ad­dress pins have no eff ect.

When writing t o the semap hore , onl y I/ O
to the left port of an unused semaphore, a 1 will appear at the same
semaphore address on the right port. That semaphore can now only
be modified by the side showing 0 (the left port in this case). If the left
port now rel inquishes control by writing a 1 to the semaph ore, the
semaphore will be set to 1 for both sides. Howev er, if the right port had
requested the semaphore (written a 0) while the left port had control,

T able 3. Semaphore Operation Example

No action 1 1 Semaphore free
Left port writes semaphore 0 1 Left port obtains semaphore
Right port writes 0 to semaphore 0 1 Right side is denied access
Left port writes 1 to semaphore 1 0 Right port is granted access to semaphore
Left port writes 0 to semaphore 1 0 No change. Left port is denied access
Right port writes 1 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No por t accessing semaphore address
Right port writes 0 to semaphore 1 0 Right port obtains semaphore
Right port writes 1 to semaphore 1 1 No port accessing semaphore
Left port writes 0 to semaphore 0 1 Left port obtains semaphore
Left port writes 1 to semaphore 1 1 No por t accessing semaphore

and R/W are used in t he same manner as a norm al

LOW). A

Function I/O

represents the semaphor e

0–2

LOW. The SEM

is used. If a 0 is written

0

Left I/O

0-7/8

the right port would immediately own the semaphore as soon as the
left port released it. Table 3 shows sample semaphore operations.

When reading a semaphore, all eight data lines output the
semaphore value. The read value is latched in an output reg­ister to prevent the semaphore from changing state during a
write from the other port. If both por ts attempt to access the
semaphore withi n t
be obtained by one side or the other, but there is no guarantee which
side will control the semaphore.

Initialization of the semaphore is not automatic and must be
reset during initialization program at power-up. All Sema­phores on both sides should have a one written into them at
init ializat ion from both sides to assure t hat they will b e free
when needed.

Right Status

0-7/8

of each other, the semaphore will definitely

SPS

Ordering Information

16K x8 Dual-Port SRAM

Speed

(ns) Ordering Code

15 CY7C006-15AC A65 64-Lead Thin Quad Flat Package Co mme rcial

CY7C006-15JC J81 68-Lead Plastic Leaded Chip Carrier

25 CY7C006-25AC A65 64-Lead Thin Quad Flat Package Co mme rcial

CY7C006-25JC J81 68-Lead Plastic Leaded Chip Carrier
CY7C006-25AI A65 64-Lead Thin Quad Flat Package Industrial
CY7C006-25JI J81 68-Lead Plastic Leaded Chip Carrier

35 CY7C006-35AC A65 64-Lead Thin Quad Flat Package Co mme rcial

CY7C006-35JC J81 68-Lead Plastic Leaded Chip Carrier
CY7C006-35AI A65 64-Lead Thin Quad Flat Package Industrial
CY7C006-35JI J81 68-Lead Plastic Leaded Chip Carrier

55 CY7C006-55AC A65 64-Lead Thin Quad Flat Package Co mme rcial

CY7C006-55JC J81 68-Lead Plastic Leaded Chip Carrier
CY7C006-55AI A65 64-Lead Thin Quad Flat Package Industrial
CY7C006-55JI J81 68-Lead Plastic Leaded Chip Carrier

Package

Name Pack age Type

Operating

Range

14

CY7C006
CY7C016

Ordering Information

16K x9 Dual-Port SRAM

Speed

(ns)

15 CY7C016-15AC A80 80-Lead Thin Quad Flat Package Co mme rcial
25 CY7C016-25AC A80 80-Lead Thin Quad Flat Package Co mme rcial

CY7C016-25AI A80 80-Lead Thin Quad Flat Package Industrial

35 CY7C016-35AC A80 80-Lead Thin Quad Flat Package Co mme rcial

CY7C016-35AI A80 80-Lead Thin Quad Flat Package Industrial

55 CY7C016-55AC A80 80-Lead Thin Quad Flat Package Co mme rcial

CY7C016-55AI A80 80-Lead Thin Quad Flat Package Industrial

Document #: 38-00416-B

(continued)

Ordering Code

Package

Name

Pack age Type

Package Diagrams

64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65

Operating

Range

15

51-85046-B

CY7C006
CY7C016

Package Diagrams

(continued)

80-Pin Thin Plastic Quad Flat Pack A80

51-85065-B

68-Lead Plastic Leaded Chip Carrier J81

51-85005-A

© Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it con vey or imply any lice nse under patent or other rights. Cypress Semicondu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.