Cypress Semiconductor CY2309SC-1T, CY2309SC-1H, CY2309SC-1, CY2309ZI-1HT, CY2309ZI-1H Datasheet

CY2305

CY2309

Low-cost 3.3V Zero Delay Buffer

Features

•10-MHz to 100-/133-MHz operating range, compatible with CPU and PCI bus frequencies

•Zero input-output propagation delay

•Multiple low-skew outputs

—Output-output skew less than 250 ps

—Device-device skew less than 700 ps

—One input drives five outputs (CY2305)

—One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

•Less than 200 ps cycle-cycle jitter, compatible with Pentium -based systems

•Test Mode to bypass phase-locked loop (PLL) (CY2309 only [see “Select Input Decoding” on page 2])

•Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil SOIC package (CY2305)

•3.3V operation

•Industrial temperature available

Functional Description

The CY2309 is a low-cost 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The CY2305 is an 8-pin version of the CY2309. It accepts one reference input, and drives out five low-skew clocks. The -1H versions of each device operate at

up to 100-/133-MHz frequencies, and have higher drive than the -1 devices. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad.

The CY2309 has two banks of four outputs each, which can be controlled by the Select inputs as shown in the “Select Input Decoding” table on page 2. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes.

The CY2305 and CY2309 PLLs enter a power-down mode when there are no rising edges on the REF input. In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 12.0 A of current draw for commercial temperature devices and 25.0 A for industrial temperature parts. The CY2309 PLL shuts down in one additional case as shown in the table below.

Multiple CY2305 and CY2309 devices can accept the same input clock and distribute it. In this case, the skew between the outputs of two devices is guaranteed to be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input to output propagation delay on both devices is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250 ps.

The CY2305/CY2309 is available in two/three different configurations, as shown in the ordering information (page 10). The CY2305-1/CY2309-1 is the base part. The CY2305-1H/ CY2309-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1s.

Block Diagram
PLL	MUX	CLKOUT
REF		CLKA1
		CLKA2
		CLKA3
		CLKA4

S2							CLKB1
		Select Input
							CLKB2
		Decoding
S1							CLKB3
							CLKB4
2309-1

Pin Configuration

		SOIC/TSSOP
		Top View
	REF	1	16	CLKOUT
	CLKA1	2	15	CLKA4
	CLKA2	3	14	CLKA3
	VDD	4	13	VDD
	GND	5	12	GND
	CLKB1	6	11	CLKB4
	CLKB2	7	10	CLKB3	2309-2
	S2	8	9	S1
			SOIC
			Top View

	REF	1	8	CLKOUT
	CLK2	2	7	CLK4	2309-3
		3	6	VDD
	CLK1
	GND	4	5	CLK3

Cypress Semiconductor Corporation	•	3901 North First Street	•	San Jose , CA 95134	•	408-943-2600
Document #: 38-07140 Rev. *C				Revised December 14, 2002

CY2305

CY2309

Pin Description for CY2309

Pin	Signal	Description
1	REF[1]	Input reference frequency, 5V-tolerant input
2	CLKA1[2]	Buffered clock output, Bank A
3	CLKA2[2]	Buffered clock output, Bank A
4	VDD	3.3V supply
5	GND	Ground
6	CLKB1[2]	Buffered clock output, Bank B
7	CLKB2[2]	Buffered clock output, Bank B
8	S2[3]	Select input, bit 2
9	S1[3]	Select input, bit 1
10	CLKB3[2]	Buffered clock output, Bank B
11	CLKB4[2]	Buffered clock output, Bank B
12	GND	Ground
13	VDD	3.3V supply
14	CLKA3[2]	Buffered clock output, Bank A
15	CLKA4[2]	Buffered clock output, Bank A
16	CLKOUT[2]	Buffered output, internal feedback on this pin

Pin Description for CY2305

Pin	Signal	Description
1	REF[1]	Input reference frequency, 5V-tolerant input
2	CLK2[2]	Buffered clock output
3	CLK1[2]	Buffered clock output
4	GND	Ground
5	CLK3[2]	Buffered clock output
6	VDD	3.3V supply
7	CLK4[2]	Buffered clock output
8	CLKOUT[2]	Buffered clock output, internal feedback on this pin

Select Input Decoding for CY2309

S2	S1	CLOCK A1–A4	CLOCK B1–B4	CLKOUT[4]	Output Source	PLL Shutdown
0	0	Three-state	Three-state	Driven	PLL	N
0	1	Driven	Three-state	Driven	PLL	N
1	0	Driven	Driven	Driven	Reference	Y
1	1	Driven	Driven	Driven	PLL	N

Notes:

1.Weak pull-down.

2.Weak pull-down on all outputs.

3.Weak pull-ups on these inputs.

4.This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.

Document #: 38-07140 Rev. *C

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CY2305

CY2309

REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins

Zero Delay and Skew Control

All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.

For applications requiring zero input-output delay, all outputs, including CLKOUT, must be equally loaded. Even if CLKOUT is not used, it must have a capacitive load, equal to that on

other outputs, for obtaining zero input-output delay. If input to output delay adjustments are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.

For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”

Document #: 38-07140 Rev. *C

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CY2305

CY2309

Maximum Ratings

Supply Voltage to Ground Potential	............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............	–0.5V to VDD + 0.5V
DC Input Voltage REF.........................................	–0.5V to 7V

Storage Temperature .................................	–65° C to +150° C
Junction Temperature .................................................	150° C
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................	> 2,000V

Operating Conditions for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter	Description	Min.	Max.	Unit
VDD	Supply Voltage	3.0	3.6	V
TA	Operating Temperature (Ambient Temperature)	0	70	° C
CL	Load Capacitance, below 100 MHz		30	pF
CL	Load Capacitance, from 100 MHz to 133 MHz		10	pF
CIN	Input Capacitance		7	pF
tPU	Power-up time for all VDD's to reach minimum specified voltage
	(power ramps must be monotonic)	0.05	50	ms

Electrical Characteristics for CY2305SC-XX and CY2309SC-XX Commercial Temperature Devices

Parameter	Description	Test Conditions	Min.	Max.	Unit
VIL	Input LOW Voltage[5]			0.8	V
VIH	Input HIGH Voltage[5]		2.0		V
IIL	Input LOW Current	VIN = 0V		50.0	A
IIH	Input HIGH Current	VIN = VDD		100.0	A
VOL	Output LOW Voltage[6]	IOL = 8 mA (–1)		0.4	V
		IOH = 12 mA (–1H)
VOH	Output HIGH Voltage[6]	IOH = –8 mA (–1)	2.4		V
		IOL = –12 mA (–1H)
IDD (PD mode)	Power Down Supply Current	REF = 0 MHz		12.0	A
IDD	Supply Current	Unloaded outputs at 66.67 MHz,		32.0	mA
		SEL inputs at VDD

Switching Characteristics for CY2305SC-1and CY2309SC-1 Commercial Temperature Devices[7]

Parameter	Name	Test Conditions	Min.	Typ.	Max.	Unit
t1	Output Frequency	30-pF load	10		100	MHz
		10-pF load	10		133.33	MHz
	Duty Cycle[6] = t2 t1	Measured at 1.4V, Fout = 66.67 MHz	40.0	50.0	60.0	%
t3	Rise Time[6]	Measured between 0.8V and 2.0V			2.50	ns
t4	Fall Time[6]	Measured between 0.8V and 2.0V			2.50	ns
t5	Output to Output Skew[6]	All outputs equally loaded			250	ps
t6A	Delay, REF Rising Edge to	Measured at VDD/2		0	±350	ps
	CLKOUT Rising Edge[6]
t6B	Delay, REF Rising Edge to	Measured at VDD/2. Measured in PLL	1	5	8.7	ns
	CLKOUT Rising Edge[6]	Bypass Mode, CY2309 device only.
t7	Device to Device Skew[6]	Measured at VDD/2 on the CLKOUT pins		0	700	ps
		of devices
tJ	Cycle to Cycle Jitter[6]	Measured at 66.67 MHz, loaded outputs			200	ps
tLOCK	PLL Lock Time[6]	Stable power supply, valid clock			1.0	ms
		presented on REF pin
Notes:

5.REF input has a threshold voltage of VDD/2.

6.Parameter is guaranteed by design and characterization. Not 100% tested in production.

7.All parameters specified with loaded outputs.

Document #: 38-07140 Rev. *C

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