Cypress Semiconductor CY37256P208-125NI, CY37256P208-125NC, CY37256P160-83AI, CY37256P160-83AC, CY37256P160-154AC Datasheet

...
0 (0)

Ultra37000 CPLD Family

5V, 3.3V, ISR™ High-Performance CPLD s

Features

General Description

In-System Reprogrammable™ (ISR™) CMOS CPLDs

JTAG interface for reconfigurability

Design changes do not cause pinout changes

Design changes do not cause timing changes

High density

32 to 512 macrocells

32 to 264 I/O pins

Five dedicated inputs including four clock pins

Simple timing model

No fanout delays

No expander delays

No dedicated vs. I/O pin delays

No additional delay through PIM

No penalty for using full 16 product terms

No delay for steering or sharing product terms

3.3V and 5V versions

PCI-compatible[1]

Programmable bus-hold capabilities on all I/Os

Intelligent product term allocator provides:

0 to 16 product terms to any macrocell

Product term steering on an individual basis

Product term sharing among local macrocells

Flexible clocking

Four synchronous clocks per device

Product term clocking

Clock polarity control per logic block

Consistent package/pinout offering across all densities

Simplifies design migration

Same pinout for 3.3V and 5.0V devices

Packages

44 to 400 leads in PLCC, CLCC, PQFP, TQFP, CQFP, BGA, and Fine-Pitch BGA packages

Note:

The Ultra37000™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled system performance. The Ultra37000 family is designed to bring the flexibility, ease of use, and performance of the 22V10 to high-density CPLDs. The architecture is based on a number of logic blocks that are connected by a Programmable Interconnect Matrix (PIM). Each logic block features its own product term array, product term allocator, and 16 macrocells. The PIM distributes signals from the logic block outputs and all input pins to the logic block inputs.

All of the Ultra37000 devices are electrically erasable and InSystem Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The ISR feature provides the ability to reconfigure the devices without having design changes cause pinout or timing changes. The Cypress ISR function is implemented through a JTAGcompliant serial interface. Data is shifted in and out through the TDI and TDO pins, respectively. Because of the superior routability and simple timing model of the Ultra37000 devices, ISR allows users to change existing logic designs while simultaneously fixing pinout assignments and maintaining system performance.

The entire family features JTAG for ISR and boundary scan, and is compatible with the PCI Local Bus specification, meeting the electrical and timing requirements. The Ultra37000 family features user programmable bus-hold capabilities on all I/Os.

Ultra37000 5.0V Devices

The Ultra37000 devices operate with a 5V supply and can support 5V or 3.3V I/O levels. VCCO connections provide the capability of interfacing to either a 5V or 3.3V bus. By connecting the VCCO pins to 5V the user insures 5V TTL levels on the outputs. If VCCO is connected to 3.3V the output levels meet 3.3V JEDEC standard CMOS levels and are 5V tolerant. These devices require 5V ISR programming.

Ultra37000V 3.3V Devices

Devices operating with a 3.3V supply require 3.3V on all VCCO pins, reducing the device’s power consumption. These devices support 3.3V JEDEC standard CMOS output levels, and are 5V-tolerant. These devices allow 3.3V ISR programming.

1.Due to the 5V-tolerant nature of 3.3V device I/Os, the I/Os are not clamped to VCC, PCI VIH = 2V.

Cypress Semiconductor Corporation

3901 North First Street

San Jose , CA 95134

408-943-2600

Document #: 38-03007 Rev. *B

 

 

 

 

Revised May 7, 2003

Ultra37000 CPLD Family

Selection Guide

5.0V Selection Guide

General Information

 

 

Dedicated

 

Speed (tPD)

Speed (fMAX)

Device

Macrocells

Inputs

I/O Pins

CY37032

32

5

32

6

200

 

 

 

 

 

 

CY37064

64

5

32/64

6

200

 

 

 

 

 

 

CY37128

128

5

64/128

6.5

167

 

 

 

 

 

 

CY37192

192

5

120

7.5

154

 

 

 

 

 

 

CY37256

256

5

128/160/192

7.5

154

 

 

 

 

 

 

CY37384

384

5

160/192

10

118

 

 

 

 

 

 

CY37512

512

5

160/192/264

10

118

 

 

 

 

 

 

Speed Bins

Device

 

200

 

 

167

 

 

154

 

 

 

143

 

 

125

 

100

83

 

 

 

66

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37032

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37064

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37128

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

X

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37192

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37256

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

X

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37384

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37512

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

X

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device-Package Offering and I/O Count

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

44-

 

44-

 

44-

 

84-

84-

 

100-

 

 

160-

160-

 

208-

 

208-

 

256-

352-

Device

Lead

 

Lead

 

Lead

Lead

Lead

 

Lead

 

Lead

Lead

 

Lead

 

Lead

 

Lead

Lead

 

 

TQFP

 

PLCC

 

CLCC

PLCC

CLCC

 

TQFP

 

TQFP

CQFP

 

PQFP

 

CQFP

 

BGA

BGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37032

37

 

37

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37064

37

 

37

 

37

 

 

69

 

 

 

 

69

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37128

 

 

 

 

 

 

 

 

 

69

69

 

69

 

 

133

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37192

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37256

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

133

133

 

165

 

 

 

 

197

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37384

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

165

 

 

 

 

197

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37512

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

165

 

165

 

197

269

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3.3V Selection Guide

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

General Information

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Dedicated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

Macrocells

 

 

 

Inputs

 

 

 

 

I/O Pins

 

 

Speed (tPD)

 

 

 

Speed (fMAX)

CY37032V

 

 

32

 

 

 

 

5

 

 

 

32

 

 

 

 

8.5

 

 

 

 

143

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37064V

 

 

64

 

 

 

 

5

 

 

 

32/64

 

 

 

8.5

 

 

 

 

143

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37128V

 

 

128

 

 

 

 

5

 

 

 

64/80/128

 

 

10

 

 

 

 

125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37192V

 

 

192

 

 

 

 

5

 

 

 

120

 

 

 

 

12

 

 

 

 

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37256V

 

 

256

 

 

 

 

5

 

 

 

128/160/192

 

12

 

 

 

 

100

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37384V

 

 

384

 

 

 

 

5

 

 

 

160/192

 

 

15

 

 

 

 

83

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37512V

 

 

512

 

 

 

 

5

 

 

 

160/192/264

 

15

 

 

 

 

83

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-03007 Rev. *B

Page 2 of 63

Ultra37000 CPLD Family

Speed Bins

Device

200

167

154

143

125

100

83

66

 

 

 

 

 

 

 

 

 

CY37032V

 

 

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

CY37064V

 

 

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

CY37128V

 

 

 

X

X

 

X

 

CY37192V

 

 

 

 

 

X

 

X

 

 

 

 

 

 

 

 

 

CY37256V

 

 

 

X

 

X

 

X

CY37384V

 

 

 

 

 

 

X

X

 

 

 

 

 

 

 

 

 

CY37512V

 

 

 

 

X

 

X

X

 

 

 

 

 

 

 

 

 

Shaded areas indicate preliminary speed bins.

Device-Package Offering & I/O Count

Device

44-

Lead

TQFP

44Lead

PLCC

44Lead

CLCC

48Lead

FBGA

84Lead

PLCC

84Lead

CLCC

100Lead

TQFP

100Lead

FBGA

160Lead TQFP

160Lead CQFP

208Lead PQFP

208Lead CQFP

256Lead BGA

256Lead FBGA

352Lead BGA

400Lead FBGA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37032V

 

37

 

37

 

 

 

37

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37064V

 

37

 

37

 

37

 

37

 

69

 

 

 

69

 

69

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37128V

 

 

 

 

 

 

 

 

 

69

 

69

 

69

 

85

 

133

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37192V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

125

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37256V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

133

133

165

 

197

197

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37384V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

165

 

197

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY37512V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

165

165

197

 

269

269

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Architecture Overview of Ultra37000 Family

Programmable Interconnect Matrix

The Programmable Interconnect Matrix (PIM) consists of a completely global routing matrix for signals from I/O pins and feedbacks from the logic blocks. The PIM provides extremely robust interconnection to avoid fitting and density limitations.

The inputs to the PIM consist of all I/O and dedicated input pins and all macrocell feedbacks from within the logic blocks. The number of PIM inputs increases with pin count and the number of logic blocks. The outputs from the PIM are signals routed to the appropriate logic blocks. Each logic block receives 36 inputs from the PIM and their complements, allowing for 32-bit operations to be implemented in a single pass through the device. The wide number of inputs to the logic block also improves the routing capacity of the Ultra37000 family.

An important feature of the PIM is its simple timing. The propagation delay through the PIM is accounted for in the timing specifications for each device. There is no additional delay for traveling through the PIM. In fact, all inputs travel through the PIM. As a result, there are no route-dependent timing parameters on the Ultra37000 devices. The worst-case PIM delays are incorporated in all appropriate Ultra37000 specifications.

Routing signals through the PIM is completely invisible to the user. All routing is accomplished by software—no hand routing is necessary. Warp™ and third-party development packages automatically route designs for the Ultra37000 family in a matter of minutes. Finally, the rich routing resources of the Ultra37000 family accommodate last minute logic changes while maintaining fixed pin assignments.

Logic Block

The logic block is the basic building block of the Ultra37000 architecture. It consists of a product term array, an intelligent product-term allocator, 16 macrocells, and a number of I/O cells. The number of I/O cells varies depending on the device used. Refer to Figure 1 for the block diagram.

Product Term Array

Each logic block features a 72 x 87 programmable product term array. This array accepts 36 inputs from the PIM, which originate from macrocell feedbacks and device pins. Active LOW and active HIGH versions of each of these inputs are generated to create the full 72-input field. The 87 product terms in the array can be created from any of the 72 inputs.

Of the 87 product terms, 80 are for general-purpose use for the 16 macrocells in the logic block. Four of the remaining seven product terms in the logic block are output enable (OE) product terms. Each of the OE product terms controls up to eight of the 16 macrocells and is selectable on an individual macrocell basis. In other words, each I/O cell can select between one of two OE product terms to control the output buffer. The first two of these four OE product terms are available to the upper half of the I/O macrocells in a logic block. The other two OE product terms are available to the lower half of the I/O macrocells in a logic block.

The next two product terms in each logic block are dedicated asynchronous set and asynchronous reset product terms. The final product term is the product term clock. The set, reset, OE and product term clock have polarity control to realize OR functions in a single pass through the array.

Document #: 38-03007 Rev. *B

Page 3 of 63

Ultra37000 CPLD Family

 

 

 

 

 

3

2

2

 

 

 

 

0−16

MACRO-

I/O

 

 

 

 

 

PRODUCT

CELL

CELL

 

 

 

 

 

0

0

 

 

 

 

 

TERMS

 

 

 

 

 

 

 

 

 

 

 

7

0−16

MACRO-

 

 

 

 

 

 

 

 

 

 

 

 

 

CELL

to cells

 

 

 

 

 

PRODUCT

1

2, 4, 6 8, 10, 12

 

 

 

 

 

 

 

 

 

 

TERMS

 

 

 

FROM

 

 

 

 

 

 

 

PIM

36

72 x 87

80

PRODUCT

 

 

 

 

 

 

 

 

 

PRODUCT TERM

 

TERM

 

 

 

 

 

ARRAY

 

ALLOCATOR

 

 

 

 

 

 

 

0−16

MACRO-

I/O

 

 

 

 

 

 

CELL

CELL

 

 

 

 

 

PRODUCT

14

14

 

 

 

 

 

TERMS

 

 

 

 

 

 

 

0−16

MACRO-

 

 

TO

 

 

 

PRODUCT

CELL

 

 

 

 

 

15

 

 

PIM

 

 

16

TERMS

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

Figure 1. Logic Block with 50% Buried Macrocells

Low-Power Option

Each logic block can operate in high-speed mode for critical path performance, or in low-power mode for power conservation. The logic block mode is set by the user on a logic block by logic block basis.

Product Term Allocator

Through the product term allocator, software automatically distributes product terms among the 16 macrocells in the logic block as needed. A total of 80 product terms are available from the local product term array. The product term allocator provides two important capabilities without affecting performance: product term steering and product term sharing.

variable fashion. The software automatically takes advantage of this capability—the user does not have to intervene.

Note that neither product term sharing nor product term steering have any effect on the speed of the product. All worstcase steering and sharing configurations have been incorporated in the timing specifications for the Ultra37000 devices.

Ultra37000 Macrocell

Within each logic block there are 16 macrocells. Macrocells can either be I/O Macrocells, which include an I/O Cell which is associated with an I/O pin, or buried Macrocells, which do not connect to an I/O. The combination of I/O Macrocells and buried Macrocells varies from device to device.

Product Term Steering

Product term steering is the process of assigning product terms to macrocells as needed. For example, if one macrocell requires ten product terms while another needs just three, the product term allocator will “steer” ten product terms to one macrocell and three to the other. On Ultra37000 devices, product terms are steered on an individual basis. Any number between 0 and 16 product terms can be steered to any macrocell. Note that 0 product terms is useful in cases where a particular macrocell is unused or used as an input register.

Product Term Sharing

Product term sharing is the process of using the same product term among multiple macrocells. For example, if more than one output has one or more product terms in its equation that are common to other outputs, those product terms are only programmed once. The Ultra37000 product term allocator allows sharing across groups of four output macrocells in a

Buried Macrocell

Figure 2 displays the architecture of buried macrocells. The buried macrocell features a register that can be configured as combinatorial, a D flip-flop, a T flip-flop, or a level-triggered latch.

The register can be asynchronously set or asynchronously reset at the logic block level with the separate set and reset product terms. Each of these product terms features programmable polarity. This allows the registers to be set or reset based on an AND expression or an OR expression.

Clocking of the register is very flexible. Four global synchronous clocks and a product term clock are available to clock the register. Furthermore, each clock features programmable polarity so that registers can be triggered on falling as well as rising edges (see the Clocking section). Clock polarity is chosen at the logic block level.

The buried macrocell also supports input register capability. The buried macrocell can be configured to act as an input

Document #: 38-03007 Rev. *B

Page 4 of 63

Ultra37000 CPLD Family

register (D-type or latch) whose input comes from the I/O pin associated with the neighboring macrocell. The output of all buried macrocells is sent directly to the PIM regardless of its configuration.

I/O Macrocell

Figure 2 illustrates the architecture of the I/O macrocell. The I/O macrocell supports the same functions as the buried macrocell with the addition of I/O capability. At the output of the macrocell, a polarity control mux is available to select active LOW or active HIGH signals. This has the added advantage of allowing significant logic reduction to occur in many applications.

The Ultra37000 macrocell features a feedback path to the PIM separate from the I/O pin input path. This means that if the macrocell is buried (fed back internally only), the associated I/O pin can still be used as an input.

Bus Hold Capabilities on all I/Os

Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device’s performance. As a latch, bus-hold maintains the last state of a pin when the pin is placed in a high-impedance state, thus reducing system noise in businterface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. For more information, see the application note “Understanding Bus-Hold - A Feature of Cypress CPLDs.”

Programmable Slew Rate Control

Each output has a programmable configuration bit, which sets the output slew rate to fast or slow. For designs concerned with meeting FCC emissions standards the slow edge provides for lower system noise. For designs requiring very high performance the fast edge rate provides maximum system performance.

Document #: 38-03007 Rev. *B

Page 5 of 63

Ultra37000 CPLD Family

f

 

 

I/O MACROCELL

 

 

 

 

 

 

 

FROM PTM

 

0

 

 

 

 

 

FAST

SLEW

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

016

 

 

 

 

 

 

SLOW

 

 

 

 

 

 

 

 

 

 

 

 

 

PRODUCT

 

C25

 

 

 

 

 

 

 

C26

I/O CELL

TERMS

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

O

0

O

 

 

 

 

 

D/T/L

Q

1

 

 

1

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

“0”

 

 

 

1

O

R

 

 

 

 

 

0

 

 

2

 

 

 

 

C4

“1”

1

O

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

DECODE

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

C0 C1 C24

1

 

 

 

 

 

 

 

C6 C5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

C2

C3

 

 

 

 

 

 

 

 

BURIED MACROCELL

 

 

 

 

 

 

 

FROM PTM

 

0

 

 

 

 

 

 

 

 

 

016

 

1

 

 

 

 

 

 

 

 

 

PRODUCT

 

 

 

 

 

 

 

 

 

 

 

TERMS

 

C25

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

0

O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O

 

P

 

 

 

 

 

 

 

 

 

1

 

 

1

 

 

 

 

 

0

 

 

D/T/L

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Q

C7

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

DECODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C0 C1 C24

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

C2

C3

 

 

 

 

 

 

FEEDBACK TO PIM

 

 

 

 

 

 

 

 

FEEDBACK TO PIM

 

 

 

 

 

 

 

 

FEEDBACK TO PIM

 

 

 

 

 

ASYNCHRONOUS

 

 

 

 

 

 

 

 

 

 

 

BLOCK RESET

 

 

 

 

 

 

 

 

 

 

 

ASYNCHRONOUS

4 SYNCHRONOUS CLOCKS (CLK0,CLK1,CLK2,CLK3)

OE0

OE1

1 ASYNCHRONOUS CLOCK(PTCLK)

BLOCK PRESET

 

 

Figure 2. I/O and Buried Macrocells

FROM CLOCK POLARITY MUXES

 

INPUT PIN

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

1

O

TO PIM

 

 

 

 

 

2

 

 

D

 

D

 

 

0

 

 

3

 

 

 

 

Q

 

Q

 

 

1

 

 

 

 

 

O

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

C12 C13

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

C10 C11

 

 

 

 

 

 

 

 

D

Q

 

 

 

 

 

 

LE

 

 

 

 

 

Figure 3. Input Macrocell

Document #: 38-03007 Rev. *B

Page 6 of 63

 

 

 

 

 

 

 

 

Ultra37000 CPLD Family

 

 

 

 

 

 

0

 

TO CLOCK MUX ON

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

 

ALL INPUT MACROCELLS

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

INPUT/CLOCK PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

C12

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

 

 

 

 

 

 

 

O

 

 

 

 

 

 

 

 

1

TO CLOCK MUX

 

 

 

 

 

 

 

 

 

IN EACH

 

 

 

 

 

 

 

 

 

LOGIC BLOCK

 

 

 

 

 

 

0

 

C13, C14, C15

OR C16

 

 

 

 

 

 

1

O

TO PIM

 

 

 

 

 

 

 

2

CLOCK POLARITY MUX

 

 

 

 

 

 

 

 

 

 

D

D

 

 

 

FROM CLOCK

0

 

Q

3

 

 

ONE PER LOGIC BLOCK

 

 

Q

 

 

 

FOR EACH CLOCK INPUT

POLARITY INPUT

1

O

 

 

 

 

 

 

2

 

 

 

C10C11

 

 

 

CLOCK PINS

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C8 C9

D

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LE

 

 

 

 

 

 

Figure 4. Input/Clock Macrocell

Clocking

Each I/O and buried macrocell has access to four synchronous clocks (CLK0, CLK1, CLK2 and CLK3) as well as an asynchronous product term clock PTCLK. Each input macrocell has access to all four synchronous clocks.

Dedicated Inputs/Clocks

Five pins on each member of the Ultra37000 family are designated as input-only. There are two types of dedicated inputs on Ultra37000 devices: input pins and input/clock pins. Figure 3 illustrates the architecture for input pins. Four input options are available for the user: combinatorial, registered, double-registered, or latched. If a registered or latched option is selected, any one of the input clocks can be selected for control.

The Ultra37000 features:

No fanout delays

No expander delays

No dedicated vs. I/O pin delays

No additional delay through PIM

No penalty for using 0–16 product terms

No added delay for steering product terms

No added delay for sharing product terms

No routing delays

No output bypass delays

The simple timing model of the Ultra37000 family eliminates unexpected performance penalties.

Figure 4 illustrates the architecture for the input/clock pins. Like the input pins, input/clock pins can be combinatorial, registered, double-registered, or latched. In addition, these pins feed the clocking structures throughout the device. The clock path at the input has user-configurable polarity.

Product Term Clocking

In addition to the four synchronous clocks, the Ultra37000 family also has a product term clock for asynchronous clocking. Each logic block has an independent product term clock which is available to all 16 macrocells. Each product term clock also supports user configurable polarity selection.

Timing Model

One of the most important features of the Ultra37000 family is the simplicity of its timing. All delays are worst case and system performance is unaffected by the features used. Figure 5 illustrates the true timing model for the 167-MHz devices in high speed mode. For combinatorial paths, any input to any output incurs a 6.5-ns worst-case delay regardless of the amount of logic used. For synchronous systems, the input setup time to the output macrocells for any input is 3.5 ns and the clock to output time is also 4.0 ns. These measurements are for any output and synchronous clock, regardless of the logic used.

COMBINATORIAL SIGNAL

INPUT

 

tPD = 6.5 ns

OUTPUT

 

 

REGISTERED SIGNAL

 

 

 

tS = 3.5 ns

 

 

 

tCO = 4.5 ns

 

 

 

 

 

D,T,L O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INPUT

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK

Figure 5. Timing Model for CY37128

JTAG and PCI Standards

PCI Compliance

5V operation of the Ultra37000 is fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The 3.3V products meet all PCI requirements except for the output 3.3V clamp, which is in direct conflict with 5V tolerance. The Ultra37000 family’s simple and predictable timing model ensures compliance with the PCI AC specifications independent of the design.

Document #: 38-03007 Rev. *B

Page 7 of 63

Ultra37000 CPLD Family

IEEE 1149.1-compliant JTAG

The Ultra37000 family has an IEEE 1149.1 JTAG interface for both Boundary Scan and ISR.

Boundary Scan

The Ultra37000 family supports Bypass, Sample/Preload, Extest, Idcode, and Usercode boundary scan instructions. The JTAG interface is shown in Figure 6.

 

 

Instruction Register

TDI

 

TDO

 

 

TMS

JTAG

Bypass Reg.

 

 

TAP

 

TCK

CONTROLLER

Boundary Scan

 

 

 

 

idcode

 

 

Usercode

 

 

ISR Prog.

Data Registers

Figure 6. JTAG Interface

In-System Reprogramming (ISR)

In-System Reprogramming is the combination of the capability to program or reprogram a device on-board, and the ability to support design changes without changing the system timing or device pinout. This combination means design changes during debug or field upgrades do not cause board respins. The Ultra37000 family implements ISR by providing a JTAG compliant interface for on-board programming, robust routing resources for pinout flexibility, and a simple timing model for consistent system performance.

Development Software Support

Warp

Warp is a state-of-the-art compiler and complete CPLD design tool. For design entry, Warp provides an IEEE-STD-1076/1164 VHDL text editor, an IEEE-STD-1364 Verilog text editor, and a graphical finite state machine editor. It provides optimized synthesis and fitting by replacing basic circuits with ones preoptimized for the target device, by implementing logic in unused memory and by perfect communication between fitting and synthesis. To facilitate design and debugging, Warp provides graphical timing simulation and analysis.

Warp Professional

Warp Professional contains several additional features. It provides an extra method of design entry with its graphical block diagram editor. It allows up to 5 ms timing simulation instead of only 2 ms. It allows comparison of waveforms before and after design changes.

Warp Enterprise

Warp Enterprise provides even more features. It provides unlimited timing simulation and source-level behavioral

simulation as well as a debugger. It has the ability to generate graphical HDL blocks from HDL text. It can even generate testbenches.

Warp is available for PC and UNIX platforms. Some features are not available in the UNIX version. For further information see the Warp for PC, Warp for UNIX, Warp Professional and Warp Enterprise data sheets on Cypress’s web site (www.cypress.com).

Third-Party Software

Although Warp is a complete CPLD development tool on its own, it interfaces with nearly every third party EDA tool. All major third-party software vendors provide support for the Ultra37000 family of devices. Refer to the third-party software data sheet or contact your local sales office for a list of currently supported third-party vendors.

Programming

There are four programming options available for Ultra37000 devices. The first method is to use a PC with the 37000 UltraISR programming cable and software. With this method, the ISR pins of the Ultra37000 devices are routed to a connector at the edge of the printed circuit board. The 37000 UltraISR programming cable is then connected between the parallel port of the PC and this connector. A simple configuration file instructs the ISR software of the programming operations to be performed on each of the Ultra37000 devices in the system. The ISR software then automatically completes all of the necessary data manipulations required to accomplish the programming, reading, verifying, and other ISR functions. For more information on the Cypress ISR Interface, see the ISR Programming Kit data sheet (CY3700i).

The second method for programming Ultra37000 devices is on automatic test equipment (ATE). This is accomplished through a file created by the ISR software. Check the Cypress website for the latest ISR software download information.

The third programming option for Ultra37000 devices is to utilize the embedded controller or processor that already exists in the system. The Ultra37000 ISR software assists in this method by converting the device JEDEC maps into the ISR serial stream that contains the ISR instruction information and the addresses and data of locations to be programmed. The embedded controller then simply directs this ISR stream to the chain of Ultra37000 devices to complete the desired reconfiguring or diagnostic operations. Contact your local sales office for information on availability of this option.

The fourth method for programming Ultra37000 devices is to use the same programmer that is currently being used to program FLASH370i devices.

For all pinout, electrical, and timing requirements, refer to device data sheets. For ISR cable and software specifications, refer to the UltraISR kit data sheet (CY3700i).

Third-Party Programmers

As with development software, Cypress support is available on a wide variety of third-party programmers. All major thirdparty programmers (including BP Micro, Data I/O, and SMS) support the Ultra37000 family.

Document #: 38-03007 Rev. *B

Page 8 of 63

 

 

 

 

 

 

Ultra37000 CPLD Family

Logic Block Diagrams

 

 

 

 

 

 

 

 

CY37032/CY37032V

 

 

 

Clock/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Input

 

TDI

 

 

 

 

 

 

 

 

JTAG Tap

 

 

 

 

 

 

 

TCK

TDO

 

 

 

1

4

 

Controller

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

4

 

 

 

 

4

JTAGEN

 

 

 

 

 

 

 

 

16 I/Os

LOGIC

36

 

 

36

LOGIC

16 I/Os

 

 

 

 

 

 

I/O0−I/O15

BLOCK

16

PIM

16

BLOCK

I/O16−I/O31

 

A

B

 

 

 

 

 

 

 

 

 

16

 

 

 

 

16

 

 

Clock/

CY37064/CY37064V (100-Lead TQFP)

Input

Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16 I/Os

I/O0-I/O15

16 I/Os

I/O16-I/O31

TDI

JTAG Tap

TCK

Controller

TMS

 

 

1

4

 

 

4

 

 

 

4

 

 

36

 

36

 

 

LOGIC

 

 

 

LOGIC

16 I/Os

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O48-I/O63

A

 

PIM

 

D

 

 

36

36

 

 

 

 

 

 

16 I/Os

LOGIC

 

 

 

LOGIC

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O32-I/O47

B

 

 

 

C

 

32

 

 

 

32

 

TDO

 

 

 

 

 

Document #: 38-03007 Rev. *B

Page 9 of 63

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

CY37128/CY37128V (160-lead TQFP)

CLOCK

TDI

 

 

JTAG Tap

 

 

 

 

 

TCK

 

 

 

TDO

 

 

 

 

INPUTS

INPUTS

 

 

Controller

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

4

 

 

 

 

INPUT

 

INPUT/CLOCK

JTAGEN

 

MACROCELL

 

MACROCELLS

 

 

4

 

 

 

4

 

16 I/Os

LOGIC

 

 

 

LOGIC

16 I/Os

I/O0–I/O15

BLOCK

36

 

36

BLOCK

I/O112–I/O127

 

A

16

PIM

16

H

 

 

 

 

 

16 I/Os

LOGIC

36

 

36

LOGIC

16 I/Os

I/O16–I/O31

BLOCK

 

BLOCK

I/O96–I/O111

 

B

16

 

16

G

 

 

 

 

 

 

16 I/Os

LOGIC

36

 

36

LOGIC

16 I/Os

I/O32–I/O47

BLOCK

 

BLOCK

I/O80–I/O95

 

C

16

 

16

F

 

 

 

 

 

 

16 I/Os

LOGIC

36

 

36

LOGIC

16 I/Os

I/O28–I/O63

BLOCK

 

BLOCK

I/O64–I/O79

 

D

16

 

16

E

 

 

 

 

 

 

 

64

 

 

 

64

 

CY37192/CY37192V (160-lead TQFP)

 

 

 

Clock/

 

 

 

 

Input

Input

 

 

 

 

 

1

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10 I/Os

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O –I/O

 

 

 

 

BLOCK

 

16

 

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O110–I/O119

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

9

 

 

 

 

A

 

36

 

 

 

 

 

 

 

 

 

 

 

36

 

L

 

 

 

10 I/Os

 

 

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

I/O10–I/O19

 

 

 

 

BLOCK

16

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O100–I/O109

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

10 I/Os

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

I/O20–I/O29

 

 

 

 

BLOCK

16

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O90–I/O99

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

PIM

 

 

 

J

 

 

 

 

 

 

 

 

 

 

10 I/Os

 

 

 

 

36

 

 

36

 

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O30–I/O39

 

 

 

 

BLOCK

16

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O80–I/O89

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

10 I/Os

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

I/O40–I/O49

 

 

 

 

BLOCK

16

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O70–I/O79

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

10 I/Os

 

 

 

 

36

 

 

 

 

 

 

 

 

 

 

 

36

 

 

 

 

10 I/Os

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LOGIC

 

 

 

 

 

 

I/O50–I/O59

 

 

 

 

BLOCK

16

 

 

 

 

 

 

 

 

 

 

 

16

 

BLOCK

 

 

 

 

 

I/O60–I/O69

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

 

 

 

 

 

 

 

 

JTAG Tap

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-03007 Rev. *B

Page 10 of 63

 

 

 

 

 

 

 

 

 

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock/

 

 

 

 

CY37256/CY37256V (256-lead BGA)

 

 

Input

Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

4

 

 

 

 

 

 

12 I/Os

LOGIC

36

 

36

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O0−I/O11

BLOCK

16

 

16

BLOCK

I/O180−I/O191

 

 

 

 

A

36

 

36

P

 

 

 

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O12−I/O23

BLOCK

16

 

16

BLOCK

I/O168−I/O179

 

 

 

 

B

36

 

36

O

 

 

 

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O24−I/O35

BLOCK

16

 

16

BLOCK

I/O156−I/O167

 

 

 

 

C

 

 

36

N

 

 

 

 

 

 

12 I/Os

LOGIC

36

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O36−I/O47

BLOCK

16

 

16

BLOCK

I/O144−I/O155

 

 

 

 

D

36

PIM

 

M

 

 

 

 

 

 

12 I/Os

LOGIC

36

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O48−I/O59

BLOCK

16

 

16

BLOCK

I/O132−I/O143

 

 

 

 

E

36

 

36

L

 

 

 

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O60−I/O71

BLOCK

16

 

16

BLOCK

I/O120−I/O131

 

 

 

 

F

36

 

36

K

 

 

 

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O72−I/O83

BLOCK

16

 

16

BLOCK

I/O

108

−I/O

 

 

 

 

G

 

 

 

J

 

119

 

 

 

 

36

 

36

 

 

 

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

 

 

I/O

−I/O

95

BLOCK

16

 

16

BLOCK

I/O96−I/O107

 

84

 

H

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

JTAG Tap

TDO

96

 

 

 

96

 

 

 

TCK

Controller

 

 

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-03007 Rev. *B

Page 11 of 63

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

CY37384/CY37384V (256-Lead BGA)

12 I/Os

I/O0−I/O11

12 I/Os

I/O12−I/O23

12 I/Os

I/O24−I/O35

12 I/Os

I/O36−I/O47

12 I/Os

I/O48−I/O59

12 I/Os

I/O60−I/O71

12 I/Os

I/O72−I/O83

12 I/Os

I/O84−I/O95

TDI

 

 

JTAG Tap

 

 

 

 

 

TCK

 

 

 

TDO

 

 

Controller

 

TMS

 

 

 

 

 

 

 

 

 

Clock/

Input Input

1 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

4

 

36

 

 

 

 

 

 

 

 

 

36

 

 

LOGIC

 

 

 

LOGIC

 

BLOCK

16

 

16

BLOCK

 

AA

36

 

36

BL

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O168−I/O191

AB

36

 

36

BK

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O156−I/O179

AC

36

 

36

BJ

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O144−I/O167

AD

36

PIM

36

BI

 

LOGIC

LOGIC

 

 

 

 

 

BLOCK

16

 

16

BLOCK

 

AE

36

 

36

BH

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O132−I/O155

AF

36

 

36

BG

 

LOGIC

 

LOGIC

 

 

 

 

 

BLOCK

16

 

16

BLOCK

 

AG

 

 

36

BF

 

LOGIC

36

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O120−I/O143

AH

36

 

36

BE

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O108−I/O131

AI

36

 

 

BD

 

LOGIC

 

36

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O96−I/O119

AJ

36

 

 

BC

 

LOGIC

 

36

LOGIC

 

 

 

 

 

BLOCK

16

 

16

BLOCK

 

AK

36

 

36

BB

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

BLOCK

16

 

16

BLOCK

I/O96−I/O107

AL

 

 

 

BA

 

96

 

 

 

96

 

Document #: 38-03007 Rev. *B

Page 12 of 63

Cypress Semiconductor CY37256P208-125NI, CY37256P208-125NC, CY37256P160-83AI, CY37256P160-83AC, CY37256P160-154AC Datasheet

 

 

 

 

 

 

 

 

Ultra37000 CPLD Family

Logic Block Diagrams (continued)

 

 

 

 

 

 

CY37512/CY37512V (352-Lead BGA)

 

 

Input

Clock/ Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

4

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

4

 

 

 

 

LOGIC

36

 

36

LOGIC

 

 

 

12 I/Os

 

 

 

 

 

I/O0−I/O11

BLOCK

16

 

16

BLOCK

 

 

 

 

AA

36

 

36

BP

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O12−I/O23

BLOCK

16

 

16

BLOCK

I/O252−I/O263

 

 

 

AB

36

 

36

BO

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O24−I/O35

BLOCK

16

 

16

BLOCK

I/O240−I/O251

 

 

 

AC

 

 

36

BN

 

 

 

 

LOGIC

36

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O228−I/O239

 

 

 

AD

36

 

 

BM

 

 

 

12 I/Os

LOGIC

 

36

LOGIC

 

 

 

 

 

 

 

 

I/O36−I/O47

BLOCK

16

 

16

BLOCK

 

 

 

 

AE

 

 

36

BL

 

 

 

 

LOGIC

36

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O216−I/O227

 

 

 

AF

36

 

36

BK

 

 

 

12 I/Os

LOGIC

 

LOGIC

 

 

 

 

 

16

 

 

I/O48−I/O59

BLOCK

16

 

BLOCK

 

 

 

 

AG

36

 

36

BJ

 

 

 

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O204−I/O215

 

 

 

AH

36

PIM

36

BI

 

 

 

12 I/Os

LOGIC

LOGIC

 

 

 

 

 

 

 

 

I/O60−I/O71

BLOCK

16

 

16

BLOCK

 

 

 

 

AI

36

 

36

BH

 

 

 

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O192−I/O203

 

 

 

AJ

36

 

36

BG

 

 

 

12 I/Os

LOGIC

 

LOGIC

 

 

 

 

 

 

 

 

I/O72−I/O83

BLOCK

16

 

16

BLOCK

 

 

 

 

AK

36

 

36

BF

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O84−I/O95

BLOCK

16

 

16

BLOCK

I/O180−I/O191

 

 

 

AL

36

 

36

BE

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O96−I/O107

BLOCK

16

 

16

BLOCK

I/O168−I/O179

 

AM

 

BD

 

 

 

36

 

36

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O108−I/O119

BLOCK

16

 

16

BLOCK

I/O156−I/O167

 

 

 

AN

36

 

36

BC

 

 

 

12 I/Os

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

I/O120−I/O131

BLOCK

16

 

16

BLOCK

I/O144−I/O155

 

 

 

AO

36

 

36

BB

 

 

 

 

LOGIC

 

LOGIC

12 I/Os

 

 

 

 

 

 

 

 

 

BLOCK

16

 

16

BLOCK

I/O132−I/O143

 

 

 

AP

 

 

 

BA

 

 

 

 

132

 

 

 

132

 

TDI

JTAG Tap

 

 

 

 

 

 

 

TCK

TDO

 

 

 

 

 

 

Controller

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-03007 Rev. *B

 

 

 

 

 

Page 13 of 63

Ultra37000 CPLD Family

5.0V Device Characteristics

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................

–65°C to +150°C

Ambient Temperature with

 

Power Applied.............................................

–55°C to +125°C

Supply Voltage to Ground Potential ...............

–0.5V to +7.0V

DC Voltage Applied to Outputs

 

in High-Z State................................................

–0.5V to +7.0V

DC Input Voltage ............................................

–0.5V to +7.0V

DC Program Voltage.............................................

4.5 to 5.5V

Current into Outputs ....................................................

16 mA

Static Discharge Voltage...........................................

> 2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current.....................................................

> 200 mA

Operating Range[2]

 

Ambient

Junction

Output

 

 

Range

Temperature[2]

Temperature

Condition

VCC

VCCO

Commercial

0°C to +70°C

0°C to +90°C

5V

5V ± 0.25V

5V ± 0.25V

 

 

 

 

 

 

 

 

 

3.3V

5V ± 0.25V

3.3V ± 0.3V

 

 

 

 

 

 

Industrial

–40°C to +85°C

–40°C to +105°C

5V

5V± 0.5V

5V ± 0.5V

 

 

 

 

 

 

 

 

 

3.3V

5V ± 0.5V

3.3V ± 0.3V

 

 

 

 

 

 

Military[3]

–55°C to +125°C

–55°C to +130°C

5V

5V± 0.5V

5V ± 0.5V

 

 

 

3.3V

5V ± 0.5V

3.3V ± 0.3V

 

 

 

 

 

 

5.0V Device Electrical Characteristics Over the Operating Range

Parameter

Description

 

 

Test Conditions

Min.

Typ.

Max.

Unit

 

 

 

 

 

 

 

 

VOH

Output HIGH Voltage

VCC = Min.

IOH = –3.2 mA (Com’l/Ind)[4]

2.4

 

 

V

 

 

 

 

 

IOH = –2.0 mA (Mil)[4]

2.4

 

 

V

V

Output HIGH Voltage with

V

CC

= Max.

I

OH

= 0 A (Com’l)[6]

 

 

4.2

V

OHZ

Output Disabled[5]

 

 

 

 

 

 

 

 

 

 

 

 

IOH = 0 A (Ind/Mil)[6]

 

 

4.5

V

 

 

 

 

 

IOH = –100 A (Com’l)[6]

 

 

3.6

V

 

 

 

 

 

IOH = –150 A (Ind/Mil)[6]

 

 

3.6

V

V

Output LOW Voltage

V

CC

= Min.

I

OL

= 16 mA (Com’l/Ind)[4]

 

 

0.5

V

OL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOL = 12 mA (Mil)[4]

 

 

0.5

V

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for all Inputs[7]

2.0

 

VCCmax

V

V

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for all Inputs[7]

–0.5

 

0.8

V

IL

 

 

 

 

 

 

 

 

 

 

 

IIX

Input Load Current

VI = GND OR VCC, Bus-Hold Disabled

–10

 

10

A

IOZ

Output Leakage Current

VO = GND or VCC, Output Disabled, Bus-Hold Disabled

–50

 

50

A

IOS

Output Short Circuit Current[8, 5]

VCC = Max., VOUT = 0.5V

 

 

 

–30

 

–160

mA

IBHL

Input Bus-Hold LOW

VCC = Min., VIL = 0.8V

 

 

 

+75

 

 

A

 

Sustaining Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBHH

Input Bus-Hold HIGH

VCC = Min., VIH = 2.0V

 

 

 

–75

 

 

A

 

Sustaining Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBHLO

Input Bus-Hold LOW

VCC = Max.

 

 

 

 

 

+500

A

 

Overdrive Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IBHHO

Input Bus-Hold HIGH

VCC = Max.

 

 

 

 

 

–500

A

 

Overdrive Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

 

 

 

 

 

 

 

 

 

 

 

2.Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”

3.TA is the “Instant On” case temperature.

4.IOH = –2 mA, IOL = 2 mA for TDO.

5.Tested initially and after any design or process changes that may affect these parameters.

6.When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.

7.These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

8.Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.

Document #: 38-03007 Rev. *B

Page 14 of 63

Ultra37000 CPLD Family

Inductance[5]

 

 

 

44-

44-

44-

84-

84-

100-

160-

208-

 

 

 

Test

Lead

Lead

Lead

Lead

Lead

Lead

Lead

Lead

 

Parameter

Description

Conditions

TQFP

PLCC

CLCC

PLCC

CLCC

TQFP

TQFP

PQFP

Unit

 

 

 

 

 

 

 

 

 

 

 

 

L

Maximum Pin

VIN = 5.0V

2

5

2

8

5

8

9

11

nH

 

Inductance

at f = 1 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance[5]

Parameter

Description

Test Conditions

Max.

Unit

 

 

 

 

 

 

CI/O

Input/Output Capacitance

VIN = 5.0V at f = 1

MHz at TA = 25°C

10

pF

CCLK

Clock Signal Capacitance

VIN = 5.0V at f = 1

MHz at TA = 25°C

12

pF

C

Dual Function Pins[9]

V = 5.0V at f = 1

MHz at T = 25°C

16

pF

DP

 

IN

A

 

 

Endurance Characteristics[5]

 

 

 

 

Parameter

Description

Test Conditions

Min.

Typ.

Unit

 

 

 

 

 

 

N

Minimum Reprogramming Cycles

Normal Programming Conditions[2]

1,000

10,000

Cycles

3.3V Device Characteristics

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature .................................

–65°C to +150°C

Ambient Temperature with

–55°C to +125°C

Power Applied.............................................

Supply Voltage to Ground Potential ...............

–0.5V to +4.6V

DC Voltage Applied to Outputs

 

in High-Z State................................................

–0.5V to +7.0V

DC Input Voltage ............................................

–0.5V to +7.0V

DC Program Voltage.............................................

3.0 to 3.6V

Current into Outputs ......................................................

8 mA

Static Discharge Voltage............................................

>2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current......................................................

>200 mA

Operating Range[2]

Range

Ambient Temperature[2]

Junction Temperature

VCC[10]

Commercial

0°C to +70°C

0°C to +90°C

3.3V ± 0.3V

 

 

 

 

Industrial

–40°C to +85°C

–40°C to +105°C

3.3V ± 0.3V

 

 

 

 

Military[3]

–55°C to +125°C

–55°C to +130°C

3.3V ± 0.3V

3.3V Device Electrical Characteristics Over the Operating Range

 

Parameter

Description

 

 

Test Conditions

Min.

Max.

Unit

 

 

 

 

 

 

 

 

 

 

 

V

Output HIGH Voltage

V

= Min.

 

I

OH

= –4 mA (Com’l)[4]

2.4

 

V

 

OH

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOH = –3 mA (Mil)[4]

 

 

 

V

Output LOW Voltage

V

= Min.

 

I

OL

= 8 mA (Com’l)[4]

 

0.5

V

 

OL

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOL = 6 mA (Mil)[4]

 

 

 

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for

2.0

5.5

V

 

 

 

all Inputs[7]

 

 

 

 

 

 

 

 

 

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for

–0.5

0.8

V

 

 

 

all Inputs[7]

 

 

 

 

 

 

 

 

 

IIX

Input Load Current

VI = GND OR VCC, Bus-Hold Disabled

–10

10

A

IOZ

Output Leakage Current

VO = GND or VCC, Output Disabled, Bus-

–50

50

A

 

 

 

Hold Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

OS

Output Short Circuit Current[8, 5]

V

= Max., V

OUT

= 0.5V

–30

–160

mA

 

 

CC

 

 

 

 

 

 

 

IBHL

Input Bus-Hold LOW Sustaining

VCC = Min., VIL = 0.8V

+75

 

A

 

 

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

9.Dual pins are I/O with JTAG pins.

10. For CY37064VP100-143AC, CY37064VP100-143BBC, CY37064VP44-143AC, CY37064VP48-143BAC; Operating Range: VCC is 3.3V± 0.16V.

Document #: 38-03007 Rev. *B

Page 15 of 63

Ultra37000 CPLD Family

3.3V Device Electrical Characteristics Over the Operating Range (continued)

Parameter

Description

Test Conditions

Min.

Max.

Unit

 

 

 

 

 

 

IBHH

Input Bus-Hold HIGH Sustaining

VCC = Min., VIH = 2.0V

–75

 

A

 

Current

 

 

 

 

 

 

 

 

 

 

IBHLO

Input Bus-Hold LOW Overdrive

VCC = Max.

 

+500

A

 

Current

 

 

 

 

 

 

 

 

 

 

IBHHO

Input Bus-Hold HIGH Overdrive

VCC = Max.

 

–500

A

 

Current

 

 

 

 

 

 

 

 

 

 

Inductance[5]

 

 

 

44-

44-

44-

84-

84-

100-

160-

208-

 

 

 

Test

Lead

Lead

Lead

Lead

Lead

Lead

Lead

Lead

 

Parameter

Description

Conditions

TQFP

PLCC

CLCC

PLCC

CLCC

TQFP

TQFP

PQFP

Unit

 

 

 

 

 

 

 

 

 

 

 

 

L

Maximum Pin

VIN = 3.3V

2

5

2

8

5

8

9

11

nH

 

Inductance

at f = 1 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance[5]

Parameter

Description

Test Conditions

Max.

Unit

 

 

 

 

 

 

CI/O

Input/Output Capacitance

VIN = 3.3V at f = 1

MHz at TA = 25°C

8

pF

CCLK

Clock Signal Capacitance

VIN = 3.3V at f = 1

MHz at TA = 25°C

12

pF

C

Dual Functional Pins[9]

V = 3.3V at f = 1

MHz at T = 25°C

16

pF

DP

 

IN

A

 

 

Endurance Characteristics[5]

 

 

 

 

Parameter

Description

Test Conditions

Min.

Typ.

Unit

 

 

 

 

 

 

N

Minimum Reprogramming Cycles

Normal Programming Conditions[2]

1,000

10,000

Cycles

AC Characteristics

5.0V AC Test Loads and Waveforms

238Ω (COM’L)

319Ω (MIL)

5V

 

 

OUTPUT

170Ω

(COM’L)

35 pF

236Ω

(MIL)

INCLUDING

JIG AND

SCOPE

(a)

238Ω

(COM'L)

 

 

 

 

319Ω

(MIL)

 

 

ALL INPUT PULSES

 

5V

 

 

3.0V

90%

90%

OUTPUT

 

 

 

170Ω

(COM'L)

10%

10%

 

5 pF

236Ω

(MIL)

GND

 

 

 

 

 

<2 ns

 

<2 ns

INCLUDING

 

 

JIG AND

 

 

SCOPE

(b)

(c)

 

Equivalent to: THÉVENIN EQUIVALENT

 

 

 

 

 

99Ω

(COM’L)

 

OUTPUT

 

 

 

 

136Ω

(MIL) 2.08V

(COM'L)

 

 

 

 

 

 

 

2.13V

(MIL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 OR 35 pF

 

 

 

 

Document #: 38-03007 Rev. *B

Page 16 of 63

 

 

 

 

 

Ultra37000 CPLD Family

 

 

 

 

 

 

AC Characteristics

 

 

 

3.3V AC Test Loads and Waveforms

 

 

 

295Ω

(COM’L)

295Ω

(COM'L)

 

393Ω

(MIL)

393Ω

(MIL)

ALL INPUT PULSES

3.3V

 

 

3.3V

 

 

3.0V

90%

90%

OUTPUT

 

 

OUTPUT

 

 

 

340Ω

(COM’L)

340Ω

(COM'L)

10%

10%

 

 

35 pF

453Ω

(MIL)

5 pF

453Ω

(MIL)

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

<2 ns

 

<2 ns

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INCLUDING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

 

 

 

 

 

 

 

 

 

 

 

 

JIG AND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(a)

 

 

 

 

 

 

 

 

 

 

 

 

SCOPE

(b)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(c)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Equivalent to: THÉVENIN EQUIVALENT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

158Ω

(COM’L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

270Ω

(MIL) 1.77V (COM'L)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.77V (MIL)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5 OR 35 pF

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter[11]

 

 

 

 

 

 

 

 

 

 

 

 

VX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Waveform—Measurement Level

tER(–)

 

 

 

 

 

 

 

 

 

 

 

 

1.5V

 

 

VOH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5V

 

 

 

 

 

 

 

 

 

 

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tER(+)

 

 

 

 

 

 

 

 

 

 

 

 

2.6V

 

 

VOL

0.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

VX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tEA(+)

 

 

 

 

 

 

 

 

 

 

 

 

1.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VX

0.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tEA(–)

 

 

 

 

 

 

 

 

 

 

 

 

Vthe

 

 

 

 

VX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

VOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(d)

Test Waveforms

 

 

Switching Characteristics Over the Operating Range[12]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Combinatorial Mode Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

 

 

 

 

 

 

 

Input to Combinatorial Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ns

tPD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

 

 

 

 

 

 

 

Input to Output Through Transparent Input or Output Latch

 

ns

tPDL

 

 

[13, 14, 15]

 

 

 

 

 

 

 

 

 

Input to Output Through Transparent Input and Output Latches

 

ns

tPDLL

 

 

[13, 14, 15]

 

 

 

 

 

 

 

 

 

Input to Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ns

tEA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[11, 13]

 

 

 

 

 

 

 

 

 

Input to Output Disable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ns

tER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Register Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWL

 

Clock or Latch Enable Input LOW Time[8]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ns

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11.tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.

12.All AC parameters are measured with two outputs switching and 35-pF AC Test Load.

13.Logic Blocks operating in Low-Power Mode, add tLP to this spec.

14.Outputs using Slow Output Slew Rate, add tSLEW to this spec.

15.When VCCO = 3.3V, add t3.3IO to this spec.

Document #: 38-03007 Rev. *B

Page 17 of 63

 

 

 

 

 

 

 

 

 

 

 

 

 

Ultra37000 CPLD Family

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics Over the Operating Range[12] (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWH

Clock or Latch Enable Input HIGH Time[8]

 

 

 

 

 

 

 

 

 

 

ns

 

tIS

Input Register or Latch Set-up Time

 

 

 

 

 

 

 

 

 

 

 

ns

 

tIH

Input Register or Latch Hold Time

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

[13, 14, 15]

Input Register Clock or Latch Enable to Combinatorial Output

 

 

 

 

 

 

 

 

ns

 

tICO

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

Input Register Clock or Latch Enable to Output Through Transparent Output Latch

 

 

ns

 

tICOL

 

 

 

Synchronous Clocking Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[14, 15]

Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output

 

 

 

 

 

ns

 

tCO

 

 

 

 

 

 

t

[13]

Set-Up Time from Input to Sync. Clk (CLK , CLK

1

, CLK , or CLK ) or Latch Enable

 

ns

 

 

S

 

 

 

 

 

 

 

0

2

3

 

 

 

 

 

 

 

 

 

 

tH

Register or Latch Data Hold Time

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

[13, 14, 15]

Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Combinatorial Output

ns

 

tCO2

 

 

 

Delay (Through Logic Array)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13]

Output Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable to Output Synchronous

ns

 

tSCS

 

 

 

Clock (CLK0, CLK1, CLK2, or CLK3) or Latch Enable (Through Logic Array)

 

 

 

 

 

 

 

 

 

[13]

Set-Up Time from Input Through Transparent Latch to Output Register Synchronous Clock (CLK0

ns

 

tSL

 

 

 

CLK1, CLK2, or CLK3) or Latch Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

tHL

Hold Time for Input Through Transparent Latch from Output Register Synchronous Clock (CLK0,

ns

 

 

 

CLK1, CLK2, or CLK3) or Latch Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

Product Term Clocking Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

Product Term Clock or Latch Enable (PTCLK) to Output

 

 

 

 

 

 

 

 

ns

 

tCOPT

 

 

 

 

 

 

 

 

 

tSPT

Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)

 

 

 

 

 

ns

 

tHPT

Register or Latch Data Hold Time

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

[13]

Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or

ns

 

tISPT

 

 

 

Latch Enable (PTCLK)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tIHPT

Buried Register Used as an Input Register or Latch Data Hold Time

 

 

 

 

 

 

ns

 

 

[13, 14, 15]

Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)

ns

 

tCO2PT

 

Pipelined Mode Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13]

Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous

ns

 

tICS

 

 

 

Clock (CLK0, CLK1, CLK2, or CLK3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Operating Frequency Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f

MAX1

Maximum Frequency with Internal Feedback (Lesser of 1/t , 1/(t

S

+ t ), or 1/t

CO

)[5]

MHz

 

 

 

 

 

 

 

 

 

 

 

SCS

 

H

 

 

 

 

 

 

fMAX2

Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),

MHz

 

 

 

1/(t

S

+ t

 

), or 1/t

CO

)[5]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

f

MAX3

Maximum Frequency with External Feedback (Lesser of 1/(t

+ t ) or 1/(t

+ t

WH

)[5]

MHz

 

 

 

 

 

 

 

 

 

 

 

CO

S

WL

 

 

 

 

 

 

fMAX4

Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),

MHz

 

 

 

or 1/tSCS)[5]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset/Preset Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tRW

Asynchronous Reset Width[5]

 

 

 

 

 

 

 

 

 

 

 

ns

 

tRR[13]

Asynchronous Reset Recovery Time[5]

 

 

 

 

 

 

 

 

 

 

ns

 

 

[13, 14, 15]

Asynchronous Reset to Output

 

 

 

 

 

 

 

 

 

 

 

ns

 

tRO

 

 

 

 

 

 

 

 

 

 

 

 

tPW

Asynchronous Preset Width[5]

 

 

 

 

 

 

 

 

 

 

 

ns

 

 

[13]

Asynchronous Preset Recovery Time

[5]

 

 

 

 

 

 

 

 

 

 

ns

 

tPR

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

Asynchronous Preset to Output

 

 

 

 

 

 

 

 

 

 

 

ns

 

tPO

 

 

 

 

 

 

 

 

 

 

 

 

User Option Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tLP

Low Power Adder

 

 

 

 

 

 

 

 

 

 

 

 

ns

 

tSLEW

Slow Output Slew Rate Adder

 

 

 

 

 

 

 

 

 

 

 

ns

 

t3.3IO

3.3V I/O Mode Timing Adder[5]

 

 

 

 

 

 

 

 

 

 

 

ns

Document #: 38-03007 Rev. *B

 

 

 

 

 

 

 

 

 

 

 

 

Page 18 of 63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ultra37000 CPLD Family

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics Over the Operating Range[12] (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

JTAG Timing Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tS JTAG

 

Set-up Time from TDI and TMS to TCK[5]

 

 

 

 

 

 

 

 

 

ns

tH JTAG

 

Hold Time on TDI and TMS[5]

 

 

 

 

 

 

 

 

 

 

 

ns

tCO JTAG

 

Falling Edge of TCK to TDO[5]

 

 

 

 

 

 

 

 

 

 

 

ns

fJTAG

 

Maximum JTAG Tap Controller Frequency[5]

 

 

 

 

 

 

 

 

 

ns

Switching Characteristics Over the Operating Range[12]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

200 MHz

 

167 MHz

154 MHz

143 MHz

125 MHz

100 MHz

83 MHz

66 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Min.

Max.

 

 

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

 

Max.

Min.

Max.

Min.

Max.

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Combinatorial Mode Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

6

 

 

 

6.5

 

7.5

 

8.5

 

10

 

 

12

 

15

 

20

 

ns

tPD

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

11

 

 

 

12.5

 

14.5

 

16

 

16.5

 

 

17

 

19

 

22

 

ns

tPDL

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

12

 

 

 

13.5

 

15.5

 

17

 

17.5

 

 

18

 

20

 

24

 

ns

tPDLL

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

8

 

 

 

8.5

 

11

 

13

 

14

 

 

16

 

19

 

24

 

ns

tEA

 

 

 

 

 

 

 

 

 

 

 

 

 

[11, 13]

 

 

8

 

 

 

8.5

 

11

 

13

 

14

 

 

16

 

19

 

24

 

ns

tER

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Register Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWL

 

2.5

 

 

2.5

 

2.5

 

2.5

 

3

 

3

 

 

4

 

5

 

 

ns

tWH

 

2.5

 

 

2.5

 

2.5

 

2.5

 

3

 

3

 

 

4

 

5

 

 

ns

tIS

 

2

 

 

2

 

2

 

2

 

2

 

2.5

 

 

3

 

4

 

 

ns

tIH

 

2

 

 

2

 

2

 

2

 

2

 

2.5

 

 

3

 

4

 

 

ns

[13, 14, 15]

 

 

11

 

 

 

11

 

11

 

12.5

 

12.5

 

 

16

 

19

 

24

 

ns

tICO

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

12

 

 

 

12

 

12

 

14

 

16

 

 

18

 

21

 

26

 

ns

tICOL

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous Clocking Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO [14, 15]

 

 

4

 

 

 

4

 

4.5

 

6

 

6.5[16]

 

 

6.5[17]

 

8[18]

 

10

 

ns

tS[13]

 

4

 

 

4

 

5

 

5

 

5.5[16]

 

6[17]

 

 

8[18]

 

10

 

 

ns

tH

 

0

 

 

0

 

0

 

0

 

0

 

0

 

 

0

 

0

 

 

ns

[13, 14, 15]

 

 

9.5

 

 

 

10

 

11

 

12

 

14

 

 

16

 

19

 

24

 

ns

tCO2

 

 

 

 

 

 

 

 

 

 

 

 

 

tSCS[13]

 

5

 

 

6

 

6.5

 

7

 

8[16]

 

10

 

 

12

 

15

 

 

ns

[13]

 

7.5

 

 

7.5

 

8.5

 

9

 

10

 

12

 

 

15

 

15

 

 

ns

tSL

 

 

 

 

 

 

 

 

 

 

 

 

tHL

 

0

 

 

0

 

0

 

0

 

0

 

0

 

 

0

 

0

 

 

ns

Product Term Clocking Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[13, 14, 15]

 

 

7

 

 

 

10

 

10

 

13

 

13

 

 

13

 

15

 

20

 

ns

tCOPT

 

 

 

 

 

 

 

 

 

 

 

 

 

tSPT

 

2.5

 

 

2.5

 

2.5

 

3

 

5

 

5.5

 

 

6

 

7

 

 

ns

tHPT

 

2.5

 

 

2.5

 

2.5

 

3

 

5

 

5.5

 

 

6

 

7

 

 

ns

[13]

 

0

 

 

0

 

0

 

0

 

0

 

0

 

 

0

 

0

 

 

ns

tISPT

 

 

 

 

 

 

 

 

 

 

 

 

tIHPT

 

6

 

 

6.5

 

6.5

 

7.5

 

9

 

11

 

 

14

 

19

 

 

ns

tCO2PT[13, 14,

 

 

12

 

 

 

14

 

15

 

19

 

19

 

 

21

 

24

 

30

 

ns

15]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pipelined Mode Parameters

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tICS[13]

 

5

 

 

6

 

6

 

7

 

8[16]

 

10

 

 

12

 

15

 

 

ns

Notes:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

16.The following values correspond to the CY37512 and CY37384 devices: tCO = 5 ns, tS = 6.5 ns, tSCS = 8.5 ns, tICS = 8.5 ns, fMAX1 = 118 MHz.

17.The following values correspond to the CY37192V and CY37256V devices: tCO = 6 ns, tS = 7 ns, fMAX2 = 143 MHz, fMAX3 = 77 MHz, and fMAX4 = 100 MHz; and for the CY37512 devices: tS = 7 ns.

18.The following values correspond to the CY37512V and CY37384V devices: tCO = 6.5 ns, tS = 9.5 ns, and fMAX2 = 105 MHz.

Document #: 38-03007 Rev. *B

Page 19 of 63

Loading...
+ 44 hidden pages