AUSTIN MT4C4001JECJ-8-IT, MT4C4001JECJ-8-883C, MT4C4001JECJ-12-IT, MT4C4001JECJ-12-XT, MT4C4001JECJ-7-883C Datasheet

...
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DRAM

MT4C4001J

Austin Semiconductor, Inc.

1 MEG x 4 DRAM

Fast Page Mode DRAM

AVAILABLE AS MILITARY

SPECIFICATIONS

SMD 5962-90847

MIL-STD-883

FEATURES

Industry standard x4 pinout, timing, functions, and packages

High-performance, CMOS silicon-gate process

Single +5V±10% power supply

Low-power, 2.5mW standby; 300mW active, typical

All inputs, outputs, and clocks are fully TTL and CMOS compatible

1,024-cycle refresh distributed across 16ms

Refresh modes: RAS\-ONLY, CAS\-BEFORE-RAS\ (CBR), and HIDDEN

FAST PAGE MODE access cycle

CBR with WE\ a HIGH (JEDEC test mode capable via WCBR)

OPTIONS

MARKING

• Timing

 

 

70ns access

-7

 

80ns access

-8

 

100ns access

-10

 

120ns access

-12

 

• Packages

 

 

Ceramic DIP (300 mil)

CN

No. 103

Ceramic DIP (400 mil)

C

No. 104

Ceramic LCC*

ECN

No. 202

Ceramic ZIP

CZ

No. 400

Ceramic SOJ

ECJ

No. 504

Ceramic Gull Wing

ECG

No. 600

*NOTE: If solder-dip and lead-attach is desired on LCC packages, lead-attach must be done prior to the solderdip operation.

For more products and information please visit our web site at www.austinsemiconductor.com

PIN ASSIGNMENT

(Top View)

20-Pin DIP (C, CN)

 

 

 

 

 

 

 

Vss

 

20-Pin SOJ (ECJ),

 

 

 

 

 

 

 

 

 

 

DQ1

1

 

 

20

 

 

 

20-Pin LCC (ECN), &

 

DQ2

2

 

 

19

 

 

DQ4

20-Pin Gull Wing (ECG)

WE\

3

 

 

18

 

 

DQ3

DQ1

 

 

1

26

 

Vss

RAS\

4

 

 

17

 

 

CAS\

 

 

 

 

 

 

 

DQ2

 

2

 

25

 

DQ4

A9

5

 

 

16

 

 

OE\

WE\

 

3

 

24

 

DQ3

 

 

 

 

RAS\

 

4

 

23

 

CAS\

A0

6

 

 

15

 

 

A8

 

 

 

 

 

 

 

A9

 

5

 

22

 

OE\

 

 

 

 

 

 

A1

7

 

 

14

 

 

A7

 

 

 

 

 

 

 

A2

8

 

 

13

 

 

A6

A0

9

 

18

 

A8

A3

9

 

 

12

 

 

A5

A1

 

10

 

17

 

A7

 

 

 

 

 

 

Vcc

10

 

 

11

 

 

A4

A2

 

11

 

16

 

A6

 

 

 

 

A3

 

12

 

15

 

A5

 

 

 

 

 

 

 

 

 

 

Vcc

 

13

 

14

 

A4

 

 

20-Pin DIP (CZ)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE\

1

 

 

2

CAS\

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ3

3

 

 

 

 

 

 

 

 

 

 

 

 

4

DQ4

 

 

 

 

 

 

 

 

Vss

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

6

DQ1

 

 

 

 

 

 

 

 

DQ2

7

 

 

 

 

 

 

 

 

 

 

 

 

8

WE\

 

 

 

 

 

 

 

RAS\

9

 

 

 

 

 

 

 

 

 

 

 

10

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

11

 

 

 

 

 

 

 

 

 

 

 

 

12

A1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

13

 

 

 

 

 

 

 

 

 

 

 

 

14

A3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vcc

15

 

 

 

 

 

 

 

 

 

 

 

 

16

A4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

17

 

 

 

 

 

 

 

 

 

 

 

 

18

A6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

19

 

 

 

 

 

 

 

 

 

 

 

 

20

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GENERAL DESCRIPTION

The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS\ is used to latch the first 10 bits and CAS\ the later 10 bits. A READ or WRITE cycle is selected with the WE\ input. A logic HIGH on WE\ dictates READ mode while a logic LOW on WE\ dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE\ or CAS\, whichever occurs last. If WE\ goes LOW prior to CAS\ going LOW, the output pin(s) remain open (High-Z) until the next CAS\ cycle. If WE\ goes LOW after data reaches the output pin(s), Qs are activated and retain the selected cell data as long as CAS\ remains low (regardless of WE\ or RAS\). This LATE WE\ pulse results in a READ-WRITE cycle. The four data inputs and four data outputs are routed through four pins using common I/O and pin direction is controlled by WE\ and OE\. FAST-PAGE- MODE operations allow faster data operations (READ, WRITE, or READ-MODIFY-WRITE) within a row address (A0-A9) defined page boundary. The FAST PAGE MODE

(continued)

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

1

 

AUSTIN MT4C4001JECJ-8-IT, MT4C4001JECJ-8-883C, MT4C4001JECJ-12-IT, MT4C4001JECJ-12-XT, MT4C4001JECJ-7-883C Datasheet

DRAM

MT4C4001J

Austin Semiconductor, Inc.

GENERAL DESCRIPTION (cont.)

cycle is always initiated with a row address strobe-in by RAS\ followed by a column address strobed-in by CAS\. CAS\ may be toggled-in by holding RAS\ LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS\ HIGH terminates the FAST PAGE MODE operation.

Returning RAS\ and CAS\ HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS\

HIGH time. Memory cell data is retained in its corrected stated by maintaining power and executing any RAS\ cycle (READ, WRITE, RAS\-ONLY, CAS\-BEFORE-RAS\, or HIDDEN REFRESH) so that all 1,024 combinations of RAS\ addresses (A0-A9) are executed at least every 16ms, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS\ addressing.

FUNCTIONAL BLOCK DIAGRAM

FAST PAGE MODE

WE\

 

 

 

DATA IN

4

DQ1

 

 

 

 

 

 

 

BUFFER

 

CAS\

 

 

 

 

DQ2

 

 

 

 

 

 

 

*EARLY-WRITE

 

 

 

DQ3

 

 

DETECTION CIRCUIT

 

DATA OUT

4

DQ4

 

 

 

 

BUFFER

 

 

 

 

 

 

4

 

 

 

NO. 2 CLOCK

 

 

 

 

 

 

GENERATOR

 

 

 

 

 

 

 

 

 

 

 

OE\

 

COLUMN

 

 

COLUMN

 

 

10

ADDRESS

10

 

 

Vcc

A0

BUFFER

 

 

DECODER

4

Vss

A1

 

 

 

1024

 

 

A2

REFRESH

 

 

SENSE AMPLIFIERS

 

A3

 

 

I/O GATING

 

 

CONTROLLER

 

 

 

 

 

A4

 

 

 

 

 

 

 

 

1024 x 4

 

 

A5

 

 

 

 

 

 

 

 

 

 

 

A6

REFRESH

 

 

 

 

 

A7

 

 

 

 

 

COUNTER

 

 

 

 

 

A8

 

 

 

 

 

 

 

ROW DECODER

 

 

 

A9

10

 

MEMORY

 

 

 

 

 

 

 

 

ROW ADDRESS

 

1024

 

 

10

10

ARRAY

 

 

 

BUFFERS (10)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RAS\

NO. 1 CLOCK

GENERATOR

NOTE: WE\ LOW prior to CAS\ LOW, EW detection circuit output is a HIGH (EARLY-WRITE) CAS\ LOW prior to WE\ LOW, EW detection circuit output is a LOW (LATE-WRITE)

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

2

 

 

 

 

 

 

 

 

 

 

 

DRAM

 

Austin Semiconductor, Inc.

 

MT4C4001J

 

 

 

 

 

TRUTH TABLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADDRESSES

DATA IN/OUT

 

FUNCTION

 

RAS\

CAS\

WE\

OE\

tR

tC

DQ1-DQ4

 

Standby

 

H

H X

X

X

X

X

High-Z

 

READ

 

L

L

H

L

ROW

COL

Data Out

 

EARLY-WRITE

 

L

L

L

X

ROW

COL

Data In

 

READ-WRITE

 

L

L

H L

L H

ROW

COL

Data Out/Data In

 

FAST-PAGE-MODE

 

1st Cycle

L

H L

H

L

ROW

COL

Data Out

 

READ

 

2nd Cycle

L

H L

H

L

n/a

COL

Data Out

 

FAST-PAGE-MODE

 

1st Cycle

L

H L

L

X

ROW

COL

Data In

 

EARLY-WRITE

 

2nd Cycle

L

H L

L

X

n/a

COL

Data In

 

FAST-PAGE-MODE

 

1st Cycle

L

H L

H L

L H

ROW

COL

Data Out/Data In

 

READ-WRITE

 

2nd Cycle

L

H L

H L

L H

n/a

COL

Data Out/Data In

 

RAS\-ONLY REFRESH

 

 

L

H

X

X

ROW

n/a

High-Z

 

HIDDEN REFRESH

 

READ

L H L

L

H

L

ROW

COL

Data Out

 

 

WRITE

L H L

L

L

X

ROW

COL

Data In

 

 

 

 

 

CAS\-BEFORE-RAS\

REFRESH

H L

L

H

X

X

X

High-Z

 

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

3

 

DRAM

MT4C4001J

Austin Semiconductor, Inc.

ABSOLUTE MAXIMUM RATINGS*

 

Voltage on Any Pin Relative to Vss.................

-1.0V to +7.0V

Storage Temperature.......................................

-65oC to +150oC

Power Dissipation.................................................................

1W

Short Circuit Output Current...........................................

50mA

Lead Temperature (soldering 5 seconds).....................

+270oC

*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS

(NOTES: 1, 3, 4, 6, 7) (-55°C < TA < 125°C; V CC

= 5V ±10%)

 

 

 

 

 

 

 

 

 

 

 

PARAMETER/CONDITION

 

SYM

 

MIN

 

 

 

MAX

UNITS

 

NOTES

Supply Voltage

 

VCC

4.5

 

 

 

5.5

 

 

V

 

 

 

Input High (Logic 1) Voltage, All Inputs

 

VIH

2.4

 

 

 

VCC+0.5

 

V

 

 

 

Input Low (Logic 0) Voltage, All Inputs

 

VIL

-0.5

 

 

 

0.8

 

 

V

 

 

 

INPUT LEAKAGE CURRENT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Any Input 0V < VIN < 5.5V Vcc = 5.5V

 

II

-5

 

 

 

5

 

 

µA

 

 

 

(All other pints not under test = 0V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT LEAKAGE CURRENT

 

IOZ

-5

 

 

 

5

 

 

µA

 

 

 

(Q is Disabled, 0V < VOUT < 5.5V) Vcc = 5.5V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT LEVELS

 

VOH

2.4

 

 

 

 

 

 

 

V

 

 

 

Output High Voltage (IOUT = -5mA)

 

 

 

 

 

 

 

 

 

 

 

 

VOL

 

 

 

 

 

0.4

 

 

V

 

 

 

Output Low Voltage (IOUT = 4.2mA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MAX

 

 

 

 

 

 

PARAMETER/CONDITION

SYM

 

-7

 

-8

 

-10

 

-12

 

UNITS

 

NOTES

STANDBY CURRENT (TTL)

ICC1

 

4

 

4

 

4

 

4

 

mA

 

 

(RAS\ = CAS\ = VIH)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

STANDBY CURRENT (CMOS)

ICC2

 

2

 

2

 

2

 

2

 

mA

 

 

(RAS\ = CAS\ = VCC -0.2V; all other inputs = VCC -0.2V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPERATING CURRENT: Random READ/WRITE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Average Power-Supply Current

ICC3

 

85

 

75

 

65

 

70

 

mA

 

3, 4

(RAS\, CAS\, Address Cycling: tRC = tRC(MIN))

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OPERATING CURRENT: FAST PAGE MODE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Average Power-Supply Current

ICC4

 

60

 

50

 

45

 

40

 

mA

 

3, 4

(RAS\ = VIL, CAS\, Address Cycling: tPC = tPC (MIN))

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFRESH CURRENT: RAS\-ONLY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Average Power-Supply Current

ICC5

 

85

 

75

 

65

 

70

 

mA

 

3

(RAS\ Cycling, CAS\ = VIH: tRC = tRC (MIN))

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REFRESH CURRENT: CAS\-BEFORE-RAS\

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Average Power-Supply Current

ICC6

 

85

 

75

 

65

 

70

 

mA

 

3, 5

(RAS\, CAS\, Address Cycling: tRC = tRC (MIN))

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DRAM

 

Austin Semiconductor, Inc.

 

 

 

 

 

MT4C4001J

 

 

 

 

 

 

 

 

 

 

 

 

CAPACITANCE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PARAMETER

 

 

SYM

 

MIN

 

 

MAX

 

 

UNITS

 

NOTES

 

 

Input Capacitance: A0-A10

 

 

CI1

 

 

 

 

 

 

7

 

 

pF

 

2

 

 

 

Input Capacitance: RAS\, CAS\, WE\, OE\

 

 

CI2

 

 

 

 

 

 

7

 

 

pF

 

2

 

 

 

Input/Output Capacitance: DQ

 

 

CIO

 

 

 

 

 

8

 

 

pF

 

2

 

 

 

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C

< TC < 125°C; V CC = 5V ±10%)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-7

 

 

-8

 

 

-10

 

 

-12

 

 

 

 

PARAMETER

 

SYM

 

MIN

 

MAX

MIN

 

MAX

MIN

 

 

MAX

 

MIN

 

MAX

UNITS

NOTES

Random READ or WRITE cycle time

 

tRC

 

130

 

 

 

150

 

 

 

190

 

 

 

 

220

 

 

ns

 

READ-WRITE cycle time

 

tRWC

 

180

 

 

 

200

 

 

 

240

 

 

 

 

255

 

 

ns

 

FAST-PAGE-MODE READ or WRITE cycle time

 

tPC

 

40

 

 

 

45

 

 

 

55

 

 

 

 

70

 

 

ns

 

FAST-PAGE-MODE READ-WRITE cycle time

 

tPRWC

 

90

 

 

 

90

 

 

 

110

 

 

 

 

140

 

 

ns

 

Access time from RAS\

 

tRAC

 

 

 

70

 

 

 

80

 

 

90

 

 

 

120

ns

14

Access time from CAS\

 

tCAC

 

 

 

20

 

 

 

20

 

 

25

 

 

 

30

ns

15

Access time from column address

 

tAA

 

 

 

35

 

 

 

40

 

 

45

 

 

 

60

ns

 

Access time from CAS\ precharge

 

tCPA

 

 

 

35

 

 

 

40

 

 

45

 

 

 

60

ns

 

RAS\ pulse width

 

tRAS

 

70

 

10,000

80

 

10,000

100

 

10,000

 

120

 

100,000

ns

 

RAS\ pulse width (FAST PAGE MODE)

 

tRASP

 

70

 

100,000

80

 

100,000

100

 

100,000

 

120

 

100,000

ns

 

RAS\ hold time

 

tRSH

 

20

 

 

 

20

 

 

 

25

 

 

 

 

30

 

 

ns

 

RAS\ precharge time

 

tRP

 

50

 

 

 

60

 

 

 

70

 

 

 

 

90

 

 

ns

 

CAS\ pulse width

 

tCAS

 

20

 

10,000

20

 

10,000

25

 

10,000

 

30

 

 

ns

 

CAS\ hold time

 

tCSH

 

70

 

 

 

80

 

 

 

100

 

 

 

 

120

 

 

ns

 

CAS\ precharge time

 

tCPN

 

10

 

 

 

10

 

 

 

12

 

 

 

 

15

 

 

ns

16

CAS\ precharge time (FAST PAGE MODE)

 

tCP

 

10

 

 

 

10

 

 

 

12

 

 

 

 

15

 

 

ns

 

RAS\ to CAS\ delay time

 

tRCD

 

20

 

50

 

20

 

60

25

 

75

 

25

 

90

ns

17

CAS\ to RAS\ precharge time

 

tCRP

 

5

 

 

 

5

 

 

 

5

 

 

 

 

10

 

 

ns

 

Row address setup time

 

tASR

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

 

Row address hold time

 

tRAH

 

10

 

 

 

10

 

 

 

15

 

 

 

 

15

 

 

ns

 

RAS\ to column address delay time

 

tRAD

 

15

 

35

 

15

 

40

20

 

50

 

20

 

60

ns

18

Column address setup time

 

tASC

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

 

Column address hold time

 

tCAH

 

15

 

 

 

15

 

 

 

20

 

 

 

 

25

 

 

ns

 

Column address hold time (referenced to RAS\)

 

tAR

 

50

 

 

 

60

 

 

 

70

 

 

 

 

85

 

 

ns

 

Column address to RAS\ lead time

 

tRAL

 

35

 

 

 

40

 

 

 

50

 

 

 

 

60

 

 

ns

 

Read command setup time

 

tRCS

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

 

Read command hold time (referenced to CAS\)

 

tRCH

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

19

Read command hold time (referenced to RAS\)

 

tRRH

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

19

CAS\ to output in Low-Z

 

tCLZ

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

 

Output buffer turn-off delay

 

tOFF

 

0

 

20

 

0

 

20

0

 

20

 

0

 

20

ns

20

WE\ command setup time

 

tWCS

 

0

 

 

 

0

 

 

 

0

 

 

 

 

0

 

 

ns

21, 27

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

5

 

DRAM

MT4C4001J

Austin Semiconductor, Inc.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(NOTES: 6, 7, 8, 9, 10, 11, 12, 13) (-55°C

< TC < 125°C; V CC = 5V ±10%)

 

 

 

 

 

 

 

 

 

-7

 

-8

 

-10

 

 

-12

 

 

PARAMETER

SYM

 

MIN

 

MAX

MIN

 

MAX

MIN

 

MAX

 

MIN

 

MAX

UNITS

NOTES

Write command hold time

tWCH

 

15

 

 

15

 

 

20

 

 

 

25

 

 

ns

 

Write command hold time (referenced to RAS\)

tWCR

 

50

 

 

60

 

 

70

 

 

 

80

 

 

ns

 

Write command pulse width

tWP

 

15

 

 

15

 

 

20

 

 

 

25

 

 

ns

 

Write command to RAS\ lead time

tRWL

 

20

 

 

20

 

 

25

 

 

 

30

 

 

ns

 

Write commend to CAS\ lead time

tCWL

 

20

 

 

20

 

 

25

 

 

 

30

 

 

ns

 

Data-in setup time

tDS

 

0

 

 

0

 

 

0

 

 

 

0

 

 

ns

22

Data-in hold time

tDH

 

12

 

 

15

 

 

18

 

 

 

25

 

 

ns

22

Data-in hold time (referenced to RAS\)

tDHR

 

50

 

 

60

 

 

70

 

 

 

90

 

 

ns

 

RAS\ to WE\ delay time

tRWD

 

95

 

 

105

 

 

130

 

 

 

140

 

 

ns

21

Column address to WE\ delay time

tAWD

 

60

 

 

65

 

 

80

 

 

 

90

 

 

ns

21

CAS\ to WE\ delay time

tCWD

 

45

 

 

45

 

 

55

 

 

 

60

 

 

ns

21

Transition time (rise or fall)

tT

 

3

 

50

3

 

50

3

 

50

 

3

 

50

ns

 

Refresh period (1,024 cycles)

tREF

 

 

 

16

 

 

16

 

 

16

 

 

 

16

ns

 

RAS\ to CAS\ precharge time

tRPC

 

0

 

 

0

 

 

0

 

 

 

0

 

 

ns

 

CAS\ setup time (CAS\-BEFORE-RAS\ REFRESH)

tCSR

 

5

 

 

10

 

 

10

 

 

 

10

 

 

ns

5

CAS\ hold time (CAS\-BEFORE-RAS\ REFRESH)

tCHR

 

10

 

 

15

 

 

20

 

 

 

25

 

 

ns

5

WE\ hold time (CAS\-BEFORE-RAS\ REFRESH)

tWRH

 

10

 

 

10

 

 

10

 

 

 

10

 

 

ns

25, 28

WE\ setup time (CAS\-BEFORE-RAS\ REFRESH)

tWRP

 

10

 

 

10

 

 

10

 

 

 

10

 

 

ns

25, 28

WE\ hold time (WCBR test cycle)

tWTH

 

10

 

 

10

 

 

10

 

 

 

10

 

 

ns

25, 28

WE\ setup time (WCBR test cycle)

tWTS

 

10

 

 

10

 

 

10

 

 

 

10

 

 

ns

25, 28

OE\ setup prior to RAS during HIDDEN REFRESH cycle

tORD

 

0

 

 

0

 

 

0

 

 

 

0

 

 

ns

 

Output disable

tOD

 

 

 

15

 

 

20

 

 

25

 

 

 

25

ns

27

Output enable

tOE

 

 

 

15

 

 

20

 

 

25

 

 

 

25

ns

23

OE\ hold time from WE\ during READ-MODIFY-WRITE cycle

tOEH

 

20

 

 

20

 

 

25

 

 

 

25

 

 

ns

26

MT4C4001J

AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.

Rev. 1.0 9/01

6

 

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