ATMEL ATV750BL-25SC, ATV750BL-25PI, ATV750BL-25PC, ATV750BL-25JI, ATV750BL-25JC Datasheet

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ATMEL ATV750BL-25SC, ATV750BL-25PI, ATV750BL-25PC, ATV750BL-25JI, ATV750BL-25JC Datasheet

Features

Advanced, High-Speed Programmable Logic Device-Superset of 22V10

Improved Performance - 7.5 ns tPD, 95 MHz External Operation

Enhanced Logic Flexibility

Backward Compatible with ATV750/L Software and Hardware

New Flip-Flop Features

D- or T-Type

Product Term or Direct Input Pin Clocking

High-Speed Erasable Programmable Logic Devices

7.5 ns Maximum Pin-to-Pin Delay

Device

ICC, Stand-By

ATV750B

125 mA

 

 

ATV750BL

15 mA

 

 

Highest Density Programmable Logic Available in a 24-Pin Package

Increased Logic Flexibility

42 Array Inputs, 20 Sum Terms and 20 Flip-Flops

Enhanced Output Logic Flexibility

All 20 Flip-Flops Feed Back Internally

10 Flip-Flops are Also Available as Outputs

Full Military, Commercial and Industrial Temperature Ranges

Logic Diagram

Description

The ATV750Bs are twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configurations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance.

(continued)

Pin Configurations

Pin Name

Function

DIP/SOIC

PLCC/LCC

 

 

CLK

Clock

 

 

IN

Logic Inputs

 

 

I/O

Bidirectional Buffers

 

 

*

No Internal Connection

 

 

VCC

+5V Supply

 

 

Top View

High-Speed

UV-Erasable

Programmable

Logic Device

ATV750B

Rev. 0301D–05/98

1

Each of the ATV750B’s 22 logic pins can be used as an input. Ten of these can be used as inputs, outputs or bidirectional I/O pins. Each flip-flop is individually configurable as either D- or T-type. Each flip-flop output is fed back into the array independently. This allows burying of all the sum terms and flip-flops.

There are 171 total product terms available. A variable format is used to assign between four to eight product terms per sum term. There are two sum terms per output, providing added flexibility. Much more logic can be replaced by this device than by any other 24-pin PLD. With 20 sum terms and flip-flops, complex state machines are easily implemented with logic to spare.

Product terms provide individual clocks and asynchronous resets for each flip-flop. Each flip-flop may also be individually configured to have direct input pin controlled clocking. Each output has its own enable product term. One product term provides a common synchronous preset for all flipflops. Register preload functions are provided to simplify testing. All registers automatically reset upon power up.

The ATV750BL is a low power device with speeds as fast as 15 ns. The ATV750BL provides the optimum low power PLD solution, with full CMOS output levels. This device significantly reduces total system power, thereby allowing bat- tery-powered operation.

Abosute Maximum Rating*

................................Temperature Under Bias

-55°C to +125°C

Storage Temperature .....................................

-65°C to +150°C

Voltage on Any Pin with

-2.0V to +7.0V(1)

Respect to Ground .........................................

Voltage on Input Pins

 

with Respect to Ground

-2.0V to +14.0V(1)

During Programming.....................................

Programming Voltage with

-2.0V to +14.0V(1)

Respect to Ground .......................................

Integrated UV Erase Dose..............................

7258 Wsec/cm2

 

 

Logic Options

Combinatorial Output

Combined Terms

 

 

 

Separate Terms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to +7.0V for pulses of less than 20 ns.

Registered Output

Combined Terms

Separate Terms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

ATV750B

 

 

 

ATV750B

Clock MUX

 

 

CKMUX

 

CKi

 

 

 

 

 

 

TO

 

 

 

 

 

 

 

 

CLK

 

 

 

 

 

LOGIC

 

 

 

 

 

 

CLOCK

 

 

 

 

 

CELL

PIN

 

 

 

 

 

PRODUCT

 

SELECT

 

 

 

 

 

TERM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Options

DC and AC Operating Conditions(1)

 

Commercial

Commercial

 

 

 

-7, -10, -15

-25

Industrial

Military

 

 

 

 

 

Operating Temperature (Case)

0°C - 70°C

0°C - 70°C

-40°C - 85°C

-55°C - 125°C

 

 

 

 

 

VCC Power Supply

5V ± 5%

5V ± 10%

5V ± 10%

5V ± 10%

 

 

 

 

 

Note: 1. See ordering information for valid speed and temperature combination.

3

DC Characteristics

Symbol

Parameter

Condition

 

 

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

ILI

Input Load Current

VIN = -0.1V to VCC + 1V

 

 

 

10

μA

ILO

Output Leakage

VOUT = -0.1V to VCC + 0.1V

 

 

 

10

μA

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-7, -10

Com.

 

125

180

mA

 

 

 

 

 

 

 

 

 

 

 

Ind.,Mil.

 

125

190

mA

 

 

 

 

 

 

 

VCC = MAX,

 

 

 

 

 

 

 

Power Supply

 

Com.

 

125

180

mA

ICC

VIN = MAX,

B-15, -25

 

 

 

 

 

Current, Standby

Ind.,Mil.

 

125

190

mA

 

Outputs Open

 

 

 

 

 

 

 

 

 

BL-15

Com.

 

15

30

mA

 

 

 

 

 

 

 

 

 

 

 

Ind.,Mil.

 

15

30

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)

Output Short

VOUT = 0.5V

 

 

 

 

-120

mA

IOS

Circuit Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low Voltage

4.5 VCC 5.5V

 

 

-0.6

 

0.8

V

VIH

Input High Voltage

 

 

 

2.0

 

VCC + 0.75

V

 

Output Low

VIN = VIH or VIL,

IOL = 16 mA

Com.,Ind.

 

 

0.5

V

VOL

IOL = 12 mA

Mil.

 

 

0.5

V

Voltage

VCC = MIN

 

 

 

IOL = 24 mA

Com.

 

 

0.8

V

 

 

 

 

 

VOH

Output High

VIN = VIH or VIL,

IOH = -100 μA

 

VCC - 0.3

 

 

V

Voltage

VCC = MIN

IOH = -4.0 mA

 

2.4

 

 

V

 

 

 

 

Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

Input Test Waveforms and

Output Test Load

Measurement Levels

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tR, tF < 3 ns (10% to 90%)

4

ATV750B

 

 

 

ATV750B

AC Waveforms, Product Term Clock(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics, Product Term Clock(1)

 

 

 

-7

 

 

-10

B/BL-15

B/BL-25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

Min

 

Max

Min

 

Max

Min

Max

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPD

 

Input or Feedback to

 

 

7.5

 

 

10

 

15

 

25

ns

 

Non-Registered Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tEA

 

Input to Output Enable

 

 

7.5

 

 

10

 

15

 

25

ns

tER

 

Input to Output Disable

 

 

7.5

 

 

10

 

15

 

25

ns

tCO

 

Clock to Output

3

 

7.5

4

 

10

5

12

6

20

ns

tCF

 

Clock to Feedback

1

 

5

4

 

7.5

5

9

5

10

ns

tS

 

Input Setup Time

3

 

 

4

 

 

8/12

 

14

 

ns

tSF

 

Feedback Setup Time

3

 

 

4

 

 

7

 

7

 

ns

tH

 

Hold Time

1

 

 

2

 

 

5/7

 

5/7

 

ns

tP

 

Clock Period

7

 

 

11

 

 

14

 

17

 

ns

tW

 

Clock Width

3.5

 

 

5.5

 

 

7

 

8.5

 

ns

 

 

External Feedback 1/(tS+tCO)

 

 

95

 

 

71

 

50/41

 

29

MHz

FMAX

 

Internal Feedback 1/(tSF+tCF)

 

 

125

 

 

86

 

62

 

58

MHz

 

 

No Feedback 1/(tP)

 

 

142

 

 

90

 

71

 

58

MHz

tAW

 

Asynchronous Reset Width

5

 

 

10

 

 

15

 

20

 

ns

tAR

 

Asynchronous Reset

3

 

 

10

 

 

15

 

20

 

ns

 

Recovery Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAP

 

Asynchronous Reset to

 

 

8

 

 

12

 

15

 

25

ns

 

Registered Output Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSP

 

Setup Time, Synchronous Preset

4

 

 

7

 

 

8

 

15

 

ns

Note: 1.

See ordering information for valid part numbers.

 

 

 

 

 

 

 

 

 

5

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