ATMEL ATV750L-25SI, ATV750L-25SC, ATV750L-25PI, ATV750L-25PC, ATV750L-25NM-883 Datasheet

...
0 (0)

Features

Third Generation Programmable Logic Structure

High-Density Replacement for Discrete Logic

High-Speed — Plus a New, Low-Power Version

Increased Logic Flexibility

42 Inputs and 20 Sum Terms

Flexible Output Logic

20 Flip-Flops - 10 Extra

All Can Be Individually Buried or 10 Output Directly

Each has Individual Asynchronous Reset and Clock Terms

Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility

Proven and Reliable High-Speed CMOS EPROM Process

2000V ESD Protection

200 mA Latchup Immunity

Reprogrammable

Tested 100% for Programmability

24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages

Logic Diagram

Description

The ATV750(L) is 100% more powerful than most other programmable logic devices in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into more usable gates.

Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed back into the array independently. This flexibility allows burying all of the sum terms and flip-flops.

There are 171 product terms available. A variable format is used to assign between four and eight product terms per sum term. There are two sum terms per output, providing added flexibility.

DIP/SOIC

Pin Configurations

 

 

IN

1

24

VCC

Pin Name

Function

IN

2

23

I/O

 

 

IN

3

22

I/O

 

 

IN

Logic Inputs

IN

4

21

I/O

IN

5

20

I/O

 

 

I/O

Bidirectional Buffers

IN

6

19

I/O

IN

7

18

I/O

 

 

*

No Internal Connection

IN

8

17

I/O

IN

9

16

I/O

 

 

IN

10

15

I/O

VCC

+5V Supply

IN

11

14

I/O

 

 

GND

12

13

IN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(continued)

PLCC/LCC

(Top View)

 

 

IN

IN

IN

*

VCC

I/O

I/O

 

 

IN

4

3

2

1

28

27

26

I/O

 

5

 

 

 

 

 

25

 

IN

6

 

 

 

 

 

24

I/O

 

IN

7

 

 

 

 

 

23

I/O

*

8

 

 

 

 

 

22

*

 

IN

9

 

 

 

 

 

21

I/O

 

IN

10

 

 

 

 

 

20

I/O

 

IN

11

13

14

15

16

17

19

I/O

 

 

12

18

 

 

 

IN

IN

GND

*

IN

I/O

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High Density UV

Erasable

Programmable

Logic Device

ATV750

ATV750L

Rev. 0024E–05/98

1

ATMEL ATV750L-25SI, ATV750L-25SC, ATV750L-25PI, ATV750L-25PC, ATV750L-25NM-883 Datasheet

The ATV750(L) has more flip-flops available than other PLDs in this density range. Complex state machines are easily implemented.

Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and

Absolute Maximum Ratings

...............................Temperature Under Bias

-55°C to + 125°C

Storage Temperature ....................................

-65°C to + 150°C

Voltage on Any Pin with

-2.0V to +7.0V(1)

Respect to Ground .........................................

Voltage on Input Pins

 

with Respect to Ground

-2.0V to +14.0V(1)

During Programming.....................................

Programming Voltage with

-2.0V to +14.0V(1)

Respect to Ground .......................................

Integrated UV Erase Dose..............................

7258 W.sec/cm2

 

 

one clock term are provided per flip-flop, with one enable term per output. One product term provides a global synchronous preset. Register preload simplifies testing. The device has an internal power up clear function.

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.

Logic Options

Combined Terms

 

 

Separate Terms

 

 

 

 

 

Combined Terms

 

 

 

Separate Terms

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Options

2

ATV750/L

 

 

 

ATV750/L

DC and AC Operating Conditions

 

 

ATV750-20

ATV750/750L-25

 

 

 

 

 

Com.

0°C - 70°C

0°C - 70°C

 

 

 

 

Operating Temperature (Case)

Ind.

-40°C - 85°C

-40°C - 85°C

 

 

 

 

 

Mil.

-55°C - 125°C

-55°C - 125°C

 

 

 

 

VCC Power Supply

 

5V ± 10%

5V ± 10%

 

 

 

 

DC Characteristics

Symbol

Parameter

Condition

 

 

Min

Typ

Max

Units

 

 

 

 

 

 

 

 

 

 

ILI

Input Load

VIN = -0.1V to VCC

+ 1V

 

 

10

μA

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ILO

Output Leakage

VOUT = -0.1V to VCC + 0.1V

 

 

10

μA

Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ATV750

Com.

 

 

120

mA

 

 

VCC = MAX,

 

 

 

 

 

 

 

Power Supply

 

Ind.,Mil.

 

 

140

mA

 

 

 

 

 

ICC

VIN = GND,

 

 

 

 

 

 

 

Current

 

 

Com.

 

1.0

12

mA

 

Outputs Open

 

 

 

 

 

 

ATV750L

 

 

 

 

 

Ind.,Mil.

 

1.0

15

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(1)

Output Short Circuit Current

VOUT = 0.5V

 

 

 

 

-120

mA

IOS

 

 

 

 

VIL

Input Low Voltage

 

 

 

 

-0.6

 

0.8

V

VIH

Input High Voltage

 

 

 

 

2.0

 

VCC +

V

 

 

 

 

 

 

0.75

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIN = VIH or VIL,

 

IOL = 12 mA Com.,Ind.

 

 

0.5

V

VOL

Output Low Voltage

 

IOL = 8 mA Mil.

 

 

0.5

V

VCC = MIN

 

 

 

 

 

 

IOL = 24 mA, Com.

 

 

1.0

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Output High Voltage

VIN = VIH or VIL,

 

IOH = -100 μA

VCC - 0.3

 

 

V

VCC = MIN

 

IOH = -4.0 mA

2.4

 

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1.

Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

 

3

AC Waveforms(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

4

ATV750/L

 

 

 

ATV750/L

AC Characteristics

 

 

 

ATV750-20

ATV750/750L-25

 

 

 

 

 

 

 

 

 

Symbol

Parameter

 

Min

Max

Min

Max

Units

 

 

 

 

 

 

 

 

tPD

Input or Feedback to Non-Registered Output

 

 

20

 

25

ns

tEA

Input to Output Enable

 

 

20

 

25

ns

tER

Input to Output Disable

 

 

20

 

25

ns

tCO

Clock to Output

 

 

20

 

22

ns

tCF

Clock to Feedback

 

5

10

5

10

ns

tS

Input Setup Time

 

10

 

12

 

ns

 

 

 

 

 

 

 

 

tSF

Feedback Setup Time

 

5

 

7

 

ns

tH

Hold Time

 

5

 

5

 

ns

tP

Clock Period

 

18

 

22

 

ns

 

 

 

 

 

 

 

 

tW

Clock Width

 

8

 

10

 

ns

 

 

 

 

 

 

 

 

FMAX

Maximum Frequency

 

 

55

 

45

MHz

tAW

Asynchronous Reset Width

 

15

 

20

 

ns

tAR

Asynchronous Reset Recovery Time

 

15

 

20

 

ns

tAP

Asynchronous Reset to Registered Output Reset

 

 

20

 

25

ns

tSP

Setup Time, Synchronous Preset

 

12

 

15

 

ns

Input Test Waveforms and

Output Test Loads

 

 

 

Measurement Levels

 

 

 

 

 

 

tR, tF < 5 ns (10% to 90%)

5

Loading...
+ 9 hidden pages