Features
•Third Generation Programmable Logic Structure
–High-Density Replacement for Discrete Logic
•High-Speed — Plus a New, Low-Power Version
•Increased Logic Flexibility
–42 Inputs and 20 Sum Terms
•Flexible Output Logic
–20 Flip-Flops - 10 Extra
–All Can Be Individually Buried or 10 Output Directly
–Each has Individual Asynchronous Reset and Clock Terms
•Multiple Feedback Paths Provide for Buried State Machines and I/O Bus Compatibility
•Proven and Reliable High-Speed CMOS EPROM Process
–2000V ESD Protection
–200 mA Latchup Immunity
•Reprogrammable
–Tested 100% for Programmability
•24-pin, 300-mil Dual-In-line and 28-Lead Surface Mount Packages
Logic Diagram
Description
The ATV750(L) is 100% more powerful than most other programmable logic devices in 24-pin packages. Increased product terms, sum terms, and flip-flops translate into more usable gates.
Each of the ATV750(L)’s twenty-two logic pins can be used as an input. Ten of these can be used as input, output, or bi-directional I/O pins. All twenty flip-flops can be fed back into the array independently. This flexibility allows burying all of the sum terms and flip-flops.
There are 171 product terms available. A variable format is used to assign between four and eight product terms per sum term. There are two sum terms per output, providing added flexibility.
DIP/SOIC
Pin Configurations
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IN |
1 |
24 |
VCC |
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Pin Name |
Function |
IN |
2 |
23 |
I/O |
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IN |
3 |
22 |
I/O |
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IN |
Logic Inputs |
IN |
4 |
21 |
I/O |
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IN |
5 |
20 |
I/O |
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I/O |
Bidirectional Buffers |
IN |
6 |
19 |
I/O |
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IN |
7 |
18 |
I/O |
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* |
No Internal Connection |
IN |
8 |
17 |
I/O |
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IN |
9 |
16 |
I/O |
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IN |
10 |
15 |
I/O |
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VCC |
+5V Supply |
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IN |
11 |
14 |
I/O |
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GND |
12 |
13 |
IN |
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(continued)
PLCC/LCC
(Top View)
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IN |
IN |
IN |
* |
VCC |
I/O |
I/O |
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IN |
4 |
3 |
2 |
1 |
28 |
27 |
26 |
I/O |
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5 |
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25 |
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IN |
6 |
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24 |
I/O |
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IN |
7 |
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23 |
I/O |
* |
8 |
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22 |
* |
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IN |
9 |
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21 |
I/O |
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IN |
10 |
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20 |
I/O |
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IN |
11 |
13 |
14 |
15 |
16 |
17 |
19 |
I/O |
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12 |
18 |
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IN |
IN |
GND |
* |
IN |
I/O |
I/O |
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High Density UV |
Erasable |
Programmable |
Logic Device |
ATV750 |
ATV750L |
Rev. 0024E–05/98 |
1 |
The ATV750(L) has more flip-flops available than other PLDs in this density range. Complex state machines are easily implemented.
Product terms are available providing asynchronous resets, flip-flop clocks, and output enables. One reset and
Absolute Maximum Ratings
...............................Temperature Under Bias |
-55°C to + 125°C |
Storage Temperature .................................... |
-65°C to + 150°C |
Voltage on Any Pin with |
-2.0V to +7.0V(1) |
Respect to Ground ......................................... |
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Voltage on Input Pins |
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with Respect to Ground |
-2.0V to +14.0V(1) |
During Programming..................................... |
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Programming Voltage with |
-2.0V to +14.0V(1) |
Respect to Ground ....................................... |
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Integrated UV Erase Dose.............................. |
7258 W.sec/cm2 |
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one clock term are provided per flip-flop, with one enable term per output. One product term provides a global synchronous preset. Register preload simplifies testing. The device has an internal power up clear function.
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note: 1. Minimum voltage is -0.6V DC, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V DC, which may overshoot to 7.0V for pulses of less than 20 ns.
Logic Options
Combined Terms |
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Separate Terms |
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Combined Terms |
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Separate Terms |
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Output Options
2 |
ATV750/L |
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ATV750/L
DC and AC Operating Conditions
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ATV750-20 |
ATV750/750L-25 |
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Com. |
0°C - 70°C |
0°C - 70°C |
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Operating Temperature (Case) |
Ind. |
-40°C - 85°C |
-40°C - 85°C |
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Mil. |
-55°C - 125°C |
-55°C - 125°C |
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VCC Power Supply |
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5V ± 10% |
5V ± 10% |
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DC Characteristics
Symbol |
Parameter |
Condition |
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Min |
Typ |
Max |
Units |
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ILI |
Input Load |
VIN = -0.1V to VCC |
+ 1V |
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10 |
μA |
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Current |
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ILO |
Output Leakage |
VOUT = -0.1V to VCC + 0.1V |
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10 |
μA |
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Current |
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ATV750 |
Com. |
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120 |
mA |
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VCC = MAX, |
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Power Supply |
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Ind.,Mil. |
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140 |
mA |
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ICC |
VIN = GND, |
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Current |
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Com. |
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1.0 |
12 |
mA |
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Outputs Open |
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ATV750L |
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Ind.,Mil. |
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1.0 |
15 |
mA |
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(1) |
Output Short Circuit Current |
VOUT = 0.5V |
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-120 |
mA |
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IOS |
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VIL |
Input Low Voltage |
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-0.6 |
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0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
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VCC + |
V |
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0.75 |
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VIN = VIH or VIL, |
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IOL = 12 mA Com.,Ind. |
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0.5 |
V |
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VOL |
Output Low Voltage |
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IOL = 8 mA Mil. |
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0.5 |
V |
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VCC = MIN |
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IOL = 24 mA, Com. |
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1.0 |
V |
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VOH |
Output High Voltage |
VIN = VIH or VIL, |
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IOH = -100 μA |
VCC - 0.3 |
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V |
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VCC = MIN |
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IOH = -4.0 mA |
2.4 |
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V |
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Note: 1. |
Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. |
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3
AC Waveforms(1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
4 |
ATV750/L |
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ATV750/L
AC Characteristics
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ATV750-20 |
ATV750/750L-25 |
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Symbol |
Parameter |
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Min |
Max |
Min |
Max |
Units |
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tPD |
Input or Feedback to Non-Registered Output |
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20 |
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25 |
ns |
tEA |
Input to Output Enable |
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20 |
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25 |
ns |
tER |
Input to Output Disable |
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20 |
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25 |
ns |
tCO |
Clock to Output |
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20 |
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22 |
ns |
tCF |
Clock to Feedback |
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5 |
10 |
5 |
10 |
ns |
tS |
Input Setup Time |
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10 |
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12 |
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ns |
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tSF |
Feedback Setup Time |
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5 |
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7 |
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ns |
tH |
Hold Time |
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5 |
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5 |
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ns |
tP |
Clock Period |
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18 |
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22 |
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ns |
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tW |
Clock Width |
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8 |
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10 |
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ns |
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FMAX |
Maximum Frequency |
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55 |
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45 |
MHz |
tAW |
Asynchronous Reset Width |
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15 |
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20 |
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ns |
tAR |
Asynchronous Reset Recovery Time |
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15 |
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20 |
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ns |
tAP |
Asynchronous Reset to Registered Output Reset |
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20 |
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25 |
ns |
tSP |
Setup Time, Synchronous Preset |
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12 |
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15 |
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ns |
Input Test Waveforms and |
Output Test Loads |
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Measurement Levels |
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tR, tF < 5 ns (10% to 90%)
5