ATMEL ATF20V8BQL-25XI, ATF20V8BQL-25XC, ATF20V8BQL-25SI, ATF20V8BQL-25SC, ATF20V8BQL-25PI Datasheet

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ATMEL ATF20V8BQL-25XI, ATF20V8BQL-25XC, ATF20V8BQL-25SI, ATF20V8BQL-25SC, ATF20V8BQL-25PI Datasheet

Features

Industry Standard Architecture

Emulates Many 24-Pin PALs ®

Low Cost Easy-to-Use Software Tools

High-Speed Electrically Erasable Programmable Logic Devices

7.5 ns Maximum Pin-to-Pin Delay

Several Power Saving Options

Device

ICC, Stand-By

ICC, Active

ATF20V8B

50 mA

55 mA

 

 

 

ATF20V8BQ

35 mA

40 mA

 

 

 

ATF20V8BQL

5 mA

20 mA

 

 

 

CMOS and TTL Compatible Inputs and Outputs

Input and I/O Pull-Up Resistors

Advanced Flash Technology

Reprogrammable

100% Tested

High Reliability CMOS Process

20 Year Data Retention

100 Erase/Write Cycles

2,000V ESD Protection

200 mA Latchup Immunity

Commercial and Industrial Temperature Ranges

Dual-in-Line and Surface Mount Packages in Standard Pinouts

Block Diagram

Pin Configurations

Pin Name

Function

 

 

CLK

Clock

 

 

I

Logic Inputs

 

 

I/O

Bidirectional Buffers

 

 

OE

Output Enable

 

 

*

No Internal Connection

 

 

VCC

+5V Supply

TSSOP Top View

CLK/IN

 

 

1

 

24

 

 

VCC

IN

 

 

2

23

 

 

IN

IN

 

 

3

22

 

 

I/O

IN

 

 

4

21

 

 

I/O

IN

 

 

5

20

 

 

I/O

IN

 

 

6

19

 

 

I/O

IN

 

 

7

18

 

 

I/O

IN

 

 

8

17

 

 

I/O

IN

 

 

9

16

 

 

I/O

IN

 

 

10

15

 

 

I/O

IN

 

 

11

14

 

 

IN

GND

 

 

12

 

 

 

 

 

 

 

13

 

 

OE/IN

 

 

 

 

 

 

 

 

 

 

DIP/SOIC

PLCC Top View

High-

Performance

EE PLD

ATF20V8B

Rev. 0407E–05/98

1

Description

The ATF20V8B is a high performance CMOS (Electrically Erasable) Programmable Logic Device (PLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 7.5 ns and power dissipation as low as 10 mA are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges, and 5V ± 5% for commercial temperature ranges.

Several low power options allow selection of the best solution for various types of power-limited applications. Each of

these options significantly reduces total system power and enhances system reliability.

The ATF20V8Bs incorporate a superset of the generic architectures, which allows direct replacement of the 20R8 family and most 24-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different modes of operation, configured automatically with software, allow highly complex logic functions to be realized.

Absolute Maximum Ratings*

Temperature Under Bias................................

-55°C to +125°C

Storage Temperature .....................................

-65°C to +150°C

Voltage on Any Pin with

-2.0V to +7.0V(1)

Respect to Ground .........................................

Voltage on Input Pins

 

with Respect to Ground

-2.0V to +14.0V(1)

During Programming.....................................

Programming Voltage with

-2.0V to +14.0V(1)

Respect to Ground .......................................

*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note: 1. Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns.Maximum output pin voltage is VCC + 0.75V DC which may overshoot to 7.0V for pulses of less than 20 ns.

DC and AC Operating Conditions

 

Commercial

Industrial

 

 

 

Operating Temperature (Case)

0°C - 70°C

-40°C - 85°C

 

 

 

VCC Power Supply

5V ± 5%

5V ± 10%

2

ATF20V8B

 

 

 

ATF20V8B

DC Characteristics

Symbol

Parameter

Condition

 

 

Min

Typ

Max

 

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

IIL

Input or I/O Low

0 VIN VIL(MAX)

 

 

 

-35

-100

 

μA

Leakage Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IIH

Input or I/O High

3.5

VIN VCC

 

 

 

 

10

 

μA

Leakage Current

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-7, -10

Com.

 

60

90

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ind.

 

60

100

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC = MAX,

 

B-15, -25

Com.

 

60

80

 

mA

 

Power Supply

 

 

 

 

 

 

 

ICC

 

Ind.

 

60

90

 

mA

VIN = MAX,

 

 

 

 

Current, Standby

 

 

 

 

 

Outputs Open

 

 

 

 

 

 

 

 

 

 

BQ-10

Com.

 

35

55

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BQL-15, -25

Com.

 

5

10

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ind.

 

5

15

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B-7, -10

Com.

 

80

110

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC = MAX,

 

Ind.

 

80

125

 

mA

 

 

 

 

 

 

 

Clocked Power

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Outputs Open,

 

 

Com.

 

60

90

 

mA

 

Supply Current

 

B-15, -25

 

 

ICC2

f = 15 MHz

 

 

 

 

 

 

 

 

Ind.

 

60

105

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BQ-10

Com.

 

40

55

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BQL-15, -25

Com.

 

20

35

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ind.

 

20

40

 

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IOS(1)

Output Short

V

 

= 0.5V

 

 

 

 

-130

 

mA

 

 

 

 

 

 

 

 

Circuit Current

OUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low Voltage

 

 

 

 

 

 

-0.5

 

0.8

 

V

VIH

Input High Voltage

 

 

 

 

 

 

2.0

 

VCC + 0.75

 

V

 

 

VIN = VIH or VIL,

 

IOL = 24 mA

Com.,

 

 

0.5

 

V

VOL

Output Low Voltage

 

Ind.

 

 

 

 

 

 

 

 

 

 

VCC

= MIN

 

 

 

 

 

 

 

 

 

 

 

IOL = 16 mA

 

 

 

0.5

 

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VOH

Output High Voltage

VIN = VIH or VIL,

 

IOH = -4.0 mA

 

2.4

 

 

 

V

VCC

= MIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: 1.

Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

 

3

AC Waveforms(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.

AC Characteristics(1)

 

 

 

 

 

 

-7

 

 

-10

 

-15

 

-25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Parameter

 

 

Min

 

Max

Min

 

Max

Min

 

Max

Min

 

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPD

 

Input or Feedback to

8 outputs switching

3

 

7.5

3

 

10

3

 

15

3

 

25

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Non-Registered Output

1 output switching

 

 

7

 

 

 

 

 

 

 

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCF

 

Clock to Feedback

 

 

 

 

3

 

 

6

 

 

8

 

 

10

ns

tCO

 

Clock to Output

 

 

2

 

5

2

 

7

2

 

10

2

 

12

ns

tS

 

Input or Feedback

 

 

5

 

 

7.5

 

 

12

 

 

15

 

 

ns

 

Setup Time

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tH

 

Hold Time

 

 

0

 

 

0

 

 

0

 

 

0

 

 

ns

tP

 

Clock Period

 

 

8

 

 

12

 

 

16

 

 

24

 

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tW

 

Clock Width

 

 

4

 

 

6

 

 

8

 

 

12

 

 

ns

 

 

External Feedback 1/(tS + tCO)

 

 

100

 

 

68

 

 

45

 

 

37

MHz

FMAX

 

Internal Feedback 1/(tS + tCF)

 

 

125

 

 

74

 

 

50

 

 

40

MHz

 

 

No Feedback 1/(tP)

 

 

 

 

125

 

 

83

 

 

62

 

 

41

MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tEA

 

Input to Output

 

 

3

 

9

3

 

10

3

 

15

3

 

20

ns

 

Enable — Product Term

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tER

 

Input to Output

 

 

2

 

9

2

 

10

2

 

15

2

 

20

ns

 

Disable —Product Term

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPZX

 

 

pin to Output Enable

 

 

2

 

6

2

 

10

2

 

15

2

 

20

ns

 

OE

 

 

tPXZ

 

 

pin to Output Disable

 

 

1.5

 

6

1.5

 

10

1.5

 

15

1.5

 

20

ns

 

OE

 

 

Note: 1.

See ordering information for valid part numbers and speed grades.

 

 

 

 

 

 

 

 

 

 

4

ATF20V8B

 

 

 

ATF20V8B

Input Test Waveforms and

Output Test Loads

 

 

 

Measurement Levels

Commercial

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tR, tF < 5 ns (10% to 90%)

Pin Capacitance

f = 1 MHz, T = 25°C (1)

 

 

Typ

 

Max

Units

Conditions

 

 

 

 

 

 

 

CIN

 

5

 

8

pF

VIN = 0V

COUT

 

6

 

8

pF

VOUT = 0V

Note:

1. Typical values for nominal supply voltage.

This parameter is only sampled and is not 100% tested.

Power Up Reset

The registers in the ATF20V8Bs are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on power-up.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:

1.The VCC rise must be monotonic,

2.After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and

3.The clock must remain stable during tPR.

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to allow loading of each register with either a high or a low. This feature will simplify testing since any state can be forced into the registers to control test sequencing. A JEDEC file with preload is generated when a source file with vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automatically by most of the approved programmers after the programming.

Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the device is secured. These bits can be used for user-specific data.

Parameter

Description

Typ

Max

Units

 

 

 

 

 

tPR

Power-Up Reset Time

600

1,000

ns

VRST

Power-Up Reset Voltage

3.8

4.5

V

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF20V8B fuse patterns. Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature remains accessible.

The security fuse should be programmed last, as its effect is immediate.

Programming/Erasing

Programming/erasing is performed using standard PLD programmers. For further information, see the Configurable Logic Databook, section titled, “CMOS PLD Programming Hardware and Software Support.”

5

Input and I/O Pull-Ups

All ATF20V8B family members have internal input and I/O pull-up resistors. Therefore, whenever inputs or I/Os are not being driven externally, they will float to VCC. This ensures that all logic array inputs are at known states.

These are relatively weak active pull-ups that can easily be overdriven by TTL-compatible drivers (see input and I/O diagrams below).

Input Diagram

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF20V8B architecture. Eight configurable macrocells can be configured as a registered output, combinatorial I/O, combinatorial output, or dedicated input.

The ATF20V8B can be configured in one of three different modes. Each mode makes the ATF20V8B look like a different device. Most PLD compilers can choose the right mode automatically. The user can also force the selection by supplying the compiler with a mode selection. The determining factors would be the usage of register versus combinatorial outputs and dedicated outputs versus outputs with output enable control.

The ATF20V8B universal architecture can be programmed to emulate many 24-pin PAL devices. These architectural

I/O Diagram

subsets can be found in each of the configuration modes described in the following pages. The user can download the listed subset device JEDEC programming file to the PLD programmer, and the ATF20V8B can be configured to act like the chosen device. Check with your programmer manufacturer for this capability.

Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when programmed, protects the content of the ATF20V8B. Eight bytes (64 fuses) of User Signature are accessible to the user for purposes such as storing project name, part number, revision, or date. The User Signature is accessible regardless of the state of the Security Fuse.

6

ATF20V8B

 

 

 

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