Features |
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∙ Industry Standard Architecture |
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Emulates Many 20-Pin PALs® |
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Low Cost Easy-to-Use Software Tools |
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High Speed Electrically Erasable Programmable Logic Devices |
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5 ns Maximum Pin-to-Pin Delay |
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Low Power - 100 μA Pin-Controlled Power Down Mode Option |
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CMOS and TTL Compatible Inputs and Outputs |
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I/O Pin Keeper Circuits |
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High |
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Advanced Flash Technology |
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Reprogrammable |
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Performance |
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High Reliability CMOS Process |
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100% Tested |
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20 Year Data Retention |
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E |
2 |
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100 Erase/Write Cycles |
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PLD |
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2,000V ESD Protection |
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200 mA Latchup Immunity |
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Commercial and Industrial Temperature Ranges |
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Dual-in-Line and Surface Mount Packages in Standard Pinouts |
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ATF16V8C |
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Block Diagram |
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Note: 1. Includes optional PD control pin. |
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Pin Configurations |
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TSSOP Top View |
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Pin Name |
Function |
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CLK |
Clock |
I/CLK |
1 |
20 |
VCC |
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I |
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Logic Inputs |
I1 |
2 |
19 |
I/O |
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I/O |
Bidirectional Buffers |
I2 |
3 |
18 |
I/O |
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PD/I3 |
4 |
17 |
I/O |
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OE |
Output Enable |
I4 |
5 |
16 |
I/O |
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I5 |
6 |
15 |
I/O |
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VCC |
+5V Supply |
I6 |
7 |
14 |
I/O |
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I7 |
8 |
13 |
I/O |
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PD |
Power Down |
I8 |
9 |
12 |
I/O |
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GND |
10 |
11 |
I9/OE |
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DIP/SOIC |
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PLCC |
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Top view |
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Rev. 0425D/V16FC-D–04/98 |
Description
The ATF16V8C is a high performance EECMOS Programmable Logic Device that utilizes Atmel’s proven electrically erasable Flash memory technology. Speeds down to 5 ns and a 100 μA pin-controlled power down mode option are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges; 5V
± 5% for commercial range 5-volt devices.
The ATF16V8C incorporates a superset of the generic architectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different
Absolute Maximum Ratings*
...................Temperature Under Bias |
-40°C to +85°C |
Storage Temperature...................... |
-65°C to +150°C |
Voltage on Any Pin with |
-2.0V to +7.0V (1) |
Respect to Ground......................... |
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Voltage on Input Pins |
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with Respect to Ground |
-2.0V to +14.0V (1) |
During Programming.................... |
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Programming Voltage with |
-2.0V to +14.0V (1) |
Respect to Ground....................... |
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modes of operation, configured automatically with software, allow highly complex logic functions to be realized.
The ATF16V8C can significantly reduce total system power, thereby enhancing system reliability and reducing power supply costs. When pin 4 is configured as the power down control pin , supply current drops to less than 100 μA whenever the pin is high. If the power down feature isn’t required for a particular application, pin 4 may be used as a logic input. Also, the pin keeper circuits eliminate the need for internal pull-up resistors along with their attendant power consumption.
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1.Minimum voltage is -0.6V dc, which may undershoot to - 2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which may overshoot to 7.0V for pulses of less than 20 ns.
DC and AC Operating Conditions
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Commercial |
Industrial |
Operating Temperature (Case) |
0°C - 70°C |
-40°C - 85°C |
VCC Power Supply |
5V ± 5% |
5V ± 10% |
2 |
ATF16V8C |
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ATF16V8C
DC Characteristics
Symbol |
Parameter |
Condition |
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Min |
Typ |
Max |
Units |
IIL |
Input or I/O Low |
0 ≤ VIN ≤ VIL(MAX) |
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-10 |
μA |
Leakage Current |
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IIH |
Input or I/O High |
3.5 ≤ VIN ≤ VCC |
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10 |
μA |
Leakage Current |
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ICC1 (1) |
Power Supply Current, |
15 MHz, VCC = MAX, |
Com. |
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115 |
mA |
VIN = 0, VCC, Outputs |
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Standby |
Open |
Ind. |
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130 |
mA |
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IPD |
Power Supply Current, |
VCC = MAX, |
Com. |
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10 |
100 |
μA |
Power Down Mode |
VIN = 0, VCC |
Ind. |
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10 |
105 |
μA |
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IOS |
Output Short Circuit |
VOUT = 0.5V; |
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-150 |
mA |
Current |
VCC= 5V; TA = 25°C |
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VIL |
Input Low Voltage |
MIN < VCC < MAX |
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-0.5 |
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0.8 |
V |
VIH |
Input High Voltage |
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2.0 |
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VCC + 1 |
V |
VOL |
Output Low Voltage |
VCC = MIN; All Outputs |
Com., Ind. |
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0.5 |
V |
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IOL = 24 mA |
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VOH |
Output High Voltage |
VCC = MIN |
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2.4 |
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V |
IOL = -4.0 mA |
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IOL |
Output Low Current |
VCC = MIN |
Com. |
24 |
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mA |
Ind. |
12 |
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mA |
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IOH |
Output High Current |
VCC = MIN |
Com., Ind. |
-4 |
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mA |
Note: 1. All ICC parameters measured with outputs open. |
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AC Waveforms (1)
Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
3
AC Characteristics
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-5 |
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-7 |
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Symbol |
Parameter |
Min |
Max |
Min |
Max |
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tPD |
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Input or Feedback to Non-Registered |
1 |
5 |
3 |
7.5 |
ns |
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Output |
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tCF |
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Clock to Feedback |
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3 |
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3 |
ns |
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tCO |
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Clock to Output |
1 |
4 |
2 |
5 |
ns |
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tS |
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Input or Feedback Setup Time |
3 |
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5 |
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ns |
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tH |
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Input Hold Time |
0 |
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0 |
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ns |
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tP |
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Clock Period |
6 |
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8 |
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ns |
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tW |
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Clock Width |
3 |
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4 |
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ns |
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External Feedback 1/(tS+ tCO) |
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142 |
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100 |
MHz |
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FMAX |
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Internal Feedback 1/(tS + tCF) |
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166 |
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125 |
MHz |
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No Feedback 1/(tP) |
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166 |
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125 |
MHz |
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tEA |
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Input to Output Enable — |
2 |
6 |
3 |
9 |
ns |
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Product Term |
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tER |
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Input to Output Disable — |
2 |
5 |
2 |
9 |
ns |
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Product Term |
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tPZX |
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OE pin to Output Enable |
2 |
5 |
2 |
6 |
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tPXZ |
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OE pin to Output Disable |
1.5 |
5 |
1.5 |
6 |
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Power Down AC Characteristics (1, 2, 3)
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-5 |
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-7 |
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Symbol |
Parameter |
Min |
Max |
Min |
Max |
Units |
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tIVDH |
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Valid Input Before PD High |
5 |
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7.5 |
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ns |
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tGVDH |
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Valid OE Before PD High |
0 |
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0 |
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tCVDH |
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Valid Clock Before PD High |
0 |
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0 |
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tDHIX |
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Input Don’t Care After PD High |
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5 |
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7.5 |
ns |
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tDHGX |
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OE Don’t Care After PD High |
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5 |
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7.5 |
ns |
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tDHCX |
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Clock Don’t Care After PD High |
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5 |
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7.5 |
ns |
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tDLIV |
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PD Low to Valid Input |
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5 |
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7.5 |
ns |
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tDLGV |
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PD Low to Valid OE |
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15 |
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20 |
ns |
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tDLCV |
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PD Low to Valid Clock |
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15 |
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20 |
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tDLOV |
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PD Low to Valid Output |
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20 |
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25 |
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Notes: 1. Output data is latched and held. 2. HI-Z outputs remain HI-Z.
3. Clock and input transitions are ignored.
4 |
ATF16V8C |
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ATF16V8C |
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Input Test Waveforms and |
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Output Test Loads: |
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Measurement Levels: |
Commercial |
tR, tF < 1.5ns (10% to 90%)
Pin Capacitance |
(f = 1 MHz, T = 25°C) (1) |
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Typ |
Max |
Units |
Conditions |
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CIN |
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5 |
8 |
pF |
VIN = 0V |
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COUT |
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6 |
8 |
pF |
VOUT = 0V |
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Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power Up Reset
The ATF16V8C’s registers are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on powerup.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:
1)The VCC rise must be monotonic, from below .7 volts,
2)After reset occurs, all input and feedback setup times must be met before driving the clock term high, and
3)The signals from which the clock is derived must remain stable during tPR.
Parameter Description |
Typ |
Max |
Units |
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tPR |
Power-Up |
600 |
1,000 |
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Reset Time |
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Power-Up |
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VRST |
Reset |
3.8 |
4.5 |
V |
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Voltage |
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5