ATMEL ATF1516ASL-20UI192, ATF1516ASL-20UC192, ATF1516ASL-20QI160, ATF1516ASL-20QHI208, ATF1516ASL-20QHC208 Datasheet

...
0 (0)

Features

High Density, High Performance Electrically Erasable Complex Programmable Logic Device

256 Macrocells

5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

160, 192, 208-pins

10 ns Maximum Pin-to-Pin Delay

Registered Operation Up To 100 MHz

Enhanced Routing Resources

Flexible Logic Macrocell

D/T/Latch Configurable Flip Flops

Global and Individual Register Control Signals

Global and Individual Output Enable

Programmable Output Slew Rate

Programmable Output Open Collector Option

Maximum Logic utilization by burying a register within a COM output

Advanced Power Management Features

Automatic 3 mA Stand-By for “L” Version (Max.)

Pin-Controlled 4 mA Stand-By Mode (Typical)

Programmable Pin-Keeper Inputs and I/Os

Reduced-Power Feature Per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 160-pin PQFP, 192 PGA and 208-pin RQFP Packages

Advanced EE Technology

100% Tested

Completely Reprogrammable

100 Program/Erase Cycles

20 Year Data Retention

2000V ESD Protection

200 mA Latch-Up Immunity

JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

Fast In-System Programmability (ISP) via JTAG

PCI-compliant

3.3 or 5.0V I/O pins

Security Fuse Feature

Enhanced Features

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D - Latch Mode

Combinatorial Output with Registered Feedback within any Macrocell

Three Global Clock Pins

ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-Keeper” Option

VCC Power-Up Reset Option

Pull-Up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

Edge Controlled Power Down “L”

Individual Macrocell Power Option

Disable ITD on Global Clocks, Inputs and I/O

High

Performance

EE-Based CPLD

ATF1516AS/L

Preliminary

Rev. 0994A-A–01/98

1

ATMEL ATF1516ASL-20UI192, ATF1516ASL-20UC192, ATF1516ASL-20QI160, ATF1516ASL-20QHI208, ATF1516ASL-20QHC208 Datasheet

Block Diagram

6 to 12

 

 

P

 

O

 

N

 

M

E

L

F

K

G

J

H

I

256

 

2 ATF1516AS/L

Description

The ATF1516AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable technology. With 256 logic macrocells and up to 164 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1516AS’s enhanced routing switch matrices increase usable gate count, and increase odds of successful pin-locked design modifications.

The ATF1516AS has up to 160 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Each of the 256 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1516AS allows fast, efficient generation of complex logic functions. The ATF1516AS contains eight such

Figure 1. ATF1516AS Macrocell

ATF1516AS/L

logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms

The ATF1516AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs.

Unused Macrocells are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when pr ogrammed, protects the contents of the ATF1516AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse.

The ATF1516AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

3

Product Terms and Select MUX

Each ATF1516AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1516AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1516AS’s flip flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when the clock is low.

The clock itself can either be the Global CLK Signal (GCK) or an individual product term. The flip flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.

Output Select and Enable

The ATF1516AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 256 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block.

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 16 foldback terms in each region allows generation of high fan-in sum terms (up to 21 product terms) with a small additional delay.

4 ATF1516AS/L

Loading...
+ 7 hidden pages