ATMEL ATF1508ASZ-25QI160, ATF1508ASZ-25QI100, ATF1508ASZ-25QC160, ATF1508ASZ-25JI84, ATF1508ASZ-25JC84 Datasheet

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Features

High Density, High Performance Electrically Erasable Complex Programmable Logic Device

128 Macrocells

5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

68, 84, 100, 160-pins

7.5 ns Maximum Pin-to-Pin Delay

Registered Operation Up To 125 MHz

Enhanced Routing Resources

Flexible Logic Macrocell

D/T/Latch Configurable Flip Flops

Global and Individual Register Control Signals

Global and Individual Output Enable

Programmable Output Slew Rate

Programmable Output Open Collector Option

Maximum Logic utilization by burying a register within a COM output

Advanced Power Management Features

Automatic 100 μA Stand-By for “Z” Version (Max.)

Pin-Controlled 100 μA Stand-By Mode (Typical)

Programmable Pin-Keeper Inputs and I/Os

Reduced-Power Feature Per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 84-pin PLCC and 100-pin PQFP and TQFP and 160-pin PQFP Packages

Advanced Flash Technology

100% Tested

Completely Reprogrammable

100 Program/Erase Cycles

20 Year Data Retention

2000V ESD Protection

200 mA Latch-Up Immunity

JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

Fast In-System Programmability (ISP) via JTAG

PCI-compliant

3.3 or 5.0V I/O pins

Security Fuse Feature

Enhanced Features

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D - Latch Mode

Combinatorial Output with Registered Feedback within any Macrocell

Three Global Clock Pins

ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-Keeper” Option

VCC Power-Up Reset Option

Pull-Up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

Edge Controlled Power Down “Z”

Individual Macrocell Power Option

Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

High

Performance

E2 PLD

ATF1508AS/Z

Rev. 0784C–4/98

1

84-Lead PLCC

Top View

 

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

GND

I/O/GCLK3

I/O

I/O

VCCIO

I/O

I/O

I/O

 

I/O/PD1

11

10

9

8

7

6

5

4

3

2

1

84

83

82

81

80

79

78

77

76

75

I/O

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74

VCCIO

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

73

I/O

I/O/TDI

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

72

GND

I/O

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

71

I/O/TDO

I/O

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

I/O

I/O

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

69

I/O

I/O

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

68

I/O

GND

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

67

I/O

I/O

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

66

VCCIO

I/O

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

I/O

I/O

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

I/O

I/O/TMS

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

I/O

I/O

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

I/O/TCK

I/O

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

I/O

VCCIO

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

I/O

I/O

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

GND

I/O

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

I/O

I/O

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

I/O

I/O

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

I/O

I/O

31

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

I/O

GND

32

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

54

I/O

 

33

53

 

 

I/O

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

GND

VCCINT

I/O

I/O/PD2

I/O

GND

I/O

I/O

I/O

I/O

I/O

VCCIO

 

100-Lead TQFP

Top View

 

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

GND

I/O/GCLK3

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O

 

 

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

 

I/O/PD1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75

I/O

I/O

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74

GND

VCCIO

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

73

I/O/TDO

I/O/TDI

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

72

I/O

I/O

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

71

I/O

I/O

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

I/O

I/O

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

69

I/O

I/O

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

68

I/O

I/O

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

67

I/O

I/O

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

66

VCCIO

GND

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

I/O

I/O

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

I/O

I/O

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

I/O

I/O

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

I/O/TCK

I/O/TMS

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

I/O

I/O

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

I/O

I/O

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

GND

VCCIO

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

I/O

I/O

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

I/O

I/O

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

I/O

I/O

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

I/O

I/O

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54

I/O

I/O

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

53

I/O

I/O

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

I/O

I/O

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

VCCIO

 

26

27

28

29

30

31

33

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

 

 

GND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

GND

VCCINT

I/O

I/O/PD2

I/O

GND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

 

100-Lead PQFP

Top View

 

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

GND

I/O/GCLK3

I/O

I/O

VCCIO

I/O

I/O

I/O

 

 

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

 

I/O

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80

I/O

I/O

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

79

I/O

I/O/PD1

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

78

I/O

I/O

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

77

I/O

VCCIO

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

76

GND

I/O/TDI

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

75

I/O/TDO

I/O

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

74

I/O

I/O

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

73

I/O

I/O

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

72

I/O

I/O

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

71

I/O

I/O

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

70

I/O

I/O

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

69

I/O

GND

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

68

VCCIO

I/O

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

67

I/O

I/O

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

66

I/O

I/O

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

65

I/O

I/O/TMS

17

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

64

I/O/TCK

I/O

18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

63

I/O

I/O

19

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

62

I/O

VCCIO

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

61

GND

I/O

21

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

60

I/O

I/O

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

59

I/O

I/O

23

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

58

I/O

I/O

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

57

I/O

I/O

25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

56

I/O

I/O

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

55

I/O

I/O

27

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

54

I/O

GND

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

53

VCCIO

I/O

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

52

I/O

I/O

30

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

51

I/O

 

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

 

 

I/O

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

GND

VCCINT

I/O

I/O/PD2

I/O

GND

I/O

I/O

I/O

I/O

I/O

 

N/C 1

N/C 2

N/C 3

N/C 4

N/C 5

N/C 6

N/C 7 VCCIO 8 I/O/TDI 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

I/O 15

I/O 16

GND 17

I/O 18

I/O 19

I/O 20

I/O 21 I/O/TMS 22 I/O 23 I/O 24 I/O 25

VCCIO 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 N/C 34 N/C 35 N/C 36 N/C 37 N/C 38 N/C 39 N/C 40

160-Lead PQFP

Top View

I/O

 

I/O/PD2

 

I/O

 

N/C

 

N/C

 

N/C

 

N/C

 

I/O

 

I/O

 

I/O

 

I/O

 

I/O

 

GND

 

I/O

 

I/O

 

I/O

 

I/O

 

VCCINT

 

INPUT/OE2/GCLK2

 

INPUT/GCLR

 

INPUT/OE1

 

INPUT/GCLK1

 

GND

 

I/O/GCLK3

 

I/O

 

I/O

 

I/O

 

VCCIO

 

I/O

 

I/O

 

I/O

 

I/O

 

I/O

 

N/C

 

N/C

 

N/C

 

N/C

 

I/O

 

I/O

 

I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120 N/C

119 N/C

118 N/C

117 N/C

116 N/C

115 N/C

114 N/C

113 GND

112 I/O/TDO

111 I/O

110 I/O

109 I/O

108 I/O

107 I/O

106 I/O

105 I/O

104 VCCIO

103 I/O

102 I/O

101 I/O

100 I/O

99 I/O/TCK

98 I/O

97 I/O

96 I/O

95 GND

94 I/O

93 I/O

92 I/O

91 I/O

90 I/O

89 I/O

88 I/O

87 N/C

86 N/C

85 N/C

84 N/C

83 N/C

82 N/C

81 N/C

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

I/O

GND

I/O

N/C

N/C

N/C

N/C

I/O

I/O

I/O

I/O

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

GND

VCCINT

I/O

I/O/PD1

I/O

I/O

GND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

N/C

N/C

N/C

N/C

I/O

VCCIO

I/O

2 ATF1508AS/Z

ATMEL ATF1508ASZ-25QI160, ATF1508ASZ-25QI100, ATF1508ASZ-25QC160, ATF1508ASZ-25JI84, ATF1508ASZ-25JC84 Datasheet

ATF1508AS/Z

Block Diagram

6 to 12

3

Description

The ATF1508AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable Flash memory technology. With 128 logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. The ATF1508AS’s enhanced routing switch matrices increase usable gate count, and increase odds of successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Each of the 128 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1508AS allows fast, efficient generation of complex logic functions. The ATF1508AS contains eight such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms

The ATF1508AS macrocell, shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs.

Unused Macrocells are automatically disabled by the compiler to decrease power consumption. A Security Fuse, when pr ogrammed, protects the contents of the ATF1508AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse.

The ATF1508AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

Product Terms and Select MUX

Each ATF1508AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates

and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1508AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1508AS’s flip flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flowthrough latch. In this mode, data passes through when the clock is high and is latched when the clock is low.

The clock itself can either be the Global CLK Signal (GCK) or an individual product term. The flip flop changes state on the clock's rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.

Output Select and Enable

The ATF1508AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, includ-

4 ATF1508AS/Z

ing the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as one of the global OUTPUT enable signals. The device has six global OE signals.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 128 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block.

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the

ATF1508AS/Z

macrocell’s product terms. The 16 foldback terms in each region allows generation of high fan-in sum terms (up to 21 product terms) with a small additional delay.

3.3V or 5.0V I/O Operation

The ATF1508AS device has two sets of VCC pins viz,

VCCINT and VCCIO. VCCINT pins must always be connected to a 5.0V power supply. VCCINT pins are for input buffers and are “compatible” with both 3.3V and 5.0V inputs. V CCIO pins are for I/O output drives and can be connected for 3.3/5.0V

power supply.

Open-Collector Output Option

This option enables the device output to provide control signals such as an interrupt that can be asserted by any of the several devices.

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Figure 1. ATF1508AS Macrocell

Programmable Pin-Keeper Option for Inputs and I/Os

The ATF1508AS offers the option of programming all input and I/O pins so that “pin keeper” circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level. This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

Speed/Power Management

The ATF1508AS has several built-in speed and power management features. The ATF1508AS contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 5 - 10 MHz.

To further reduce power, each ATF1508AS macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option.

Input Diagram

 

 

I/O Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6 ATF1508AS/Z

All ATF1508s also have an optional power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power down option is selected in the design source file. When enabled, the device goes into power down when either PD1 or PD2 is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.

All Power-Down AC Characteristic parameters are computed from external input or I/O pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode (Reduced power bit turned on), the reduced power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

Design Software Support

ATF1508AS designs are supported by several third party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.

Power Up Reset

The ATF1508AS has a power-up reset option at two different voltage trip levels when the device is being powered down. Within the fitter, or during a conversion, if the “power-reset” option is turned “on” ( which is the default option), the trip levels during power up or power down is at 2.8V. The user can change this default option from “on” to “off” (within the fitter or specify it as a switch during conversion). When this is done, the voltage trip level during power-down changes from 2.8V to 0.7V. This is to ensure a robust operating environment.

The registers in the ATF1508AS are designed to reset during power up. At a point delayed slightly from VCC crossing VRST, all registers will be reset to the low state. The output state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the

ATF1508AS/Z

uncertainty of how VCC actually rises in the system, the following conditions are required:

1.The VCC rise must be monotonic,

2.After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,

3.The clock must remain stable during TPR.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1508AS fuse patterns. Once programmed, fuse verify is inhibited. However, User Signature and device ID remains accessible.

Programming

ATF1508AS devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow programming of the ATF1508AS via the PC. ISP is perfomed by using either a download cable, or a comparable board tester or a simple microprocessor interface.

To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector Format (SVF) files can be created by Atmel provided Software utilities.

ATF1508AS devices can also be programmed using standard 3rd party programmers. With 3rd party programmer the JTAG ISP port can be disabled thereby allowing 4 additional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD applications for details.

ISP Programming Protection

The ATF1508AS has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted due to any reason. The inputs and I/O default to high-Z state during such a condition. In addition the pin keeper option preserves the former state during device programming.

All ATF1508AS devices are initially shipped in the erased state thereby making them ready to use for ISP.

Note: For more information refer to the “Desigining for In-Sys- tem Programmability with Atmel CPLDs” application note.

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