ATMEL ATF1502ASL-20QC44, ATF1502ASL-20JI44, ATF1502ASL-20JC44, ATF1502ASL-20AI44, ATF1502ASL-20AC44 Datasheet

...
0 (0)

Features

High Density, High Performance Electrically Erasable Complex Programmable Logic Device

32 Macrocells

5 Product Terms per Macrocell, Expandable up to 40 per Macrocell

44 pin

7.5 ns Maximum Pin-to-Pin Delay

Registered Operation Up To 125 MHz

Enhanced Routing Resources

In-System Programmability (ISP) via JTAG

Flexible Logic Macrocell

D/T/Latch Configurable Flip Flops

Global and Individual Register Control Signals

Global and Individual Output Enable

Programmable Output Slew Rate

Programmable Output Open Collector Option

Maximum Logic utilization by burying a register with a COM output

Advanced Power Management Features

Automatic 3 mA Stand-By for “L” Version

Pin-Controlled 4 mA Stand-By Mode (Typical)

Programmable Pin-Keeper Inputs and I/Os

Reduced-Power Feature Per Macrocell

Available in Commercial and Industrial Temperature Ranges

Available in 44-pin PLCC; TQFP; and PQFP

Advanced EEPROM Technology

100% Tested

Completely Reprogrammable

100 Program/Erase Cycles

20 Year Data Retention

2000V ESD Protection

200 mA Latch-Up Immunity

JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

PCI-compliant

3.3 or 5.0V I/O pins

Security Fuse Feature

Enhanced Features

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

Output Enable Product Terms

D - Latch Mode

Combinatorial Output with Registered Feedback within any Macrocell

Three Global Clock Pins

ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

Fast Registered Input from Product Term

Programmable “Pin-Keeper” Option

VCC Power-Up Reset Option

Pull-Up Option on JTAG Pins TMS and TDI

Advanced Power Management Features

Edge Controlled Power Down “L”

Individual Macrocell Power Option

Disable ITD on Global Clocks, Inputs and I/O

High

Performance

E2PROM CPLD

ATF1502AS

Preliminary

Rev. 0995A–04/98

1

ATMEL ATF1502ASL-20QC44, ATF1502ASL-20JI44, ATF1502ASL-20JC44, ATF1502ASL-20AI44, ATF1502ASL-20AC44 Datasheet

44-Lead TQFP/PQFP

Top View

 

I/O

I/O

I/O/PD1

VCC/PD2

I/OE2/GCK2

GCLR/I

I/OE1

GCK1/I

GND

GCK3

I/O

 

 

44

43

42

41

40

39

38

37

36

35

34

 

I/O/TDI

1

 

 

 

 

 

 

 

 

 

33

I/O

I/O

2

 

 

 

 

 

 

 

 

 

32

I/O/TDO

I/O

3

 

 

 

 

 

 

 

 

 

31

I/O

GND

4

 

 

 

 

 

 

 

 

 

30

I/O

PD1/I/O

5

 

 

 

 

 

 

 

 

 

29

VCC

I/O

6

 

 

 

 

 

 

 

 

 

28

I/O

TMS/I/O

7

 

 

 

 

 

 

 

 

 

27

I/O

I/O

8

 

 

 

 

 

 

 

 

 

26

I/O/TCK

VCC

9

 

 

 

 

 

 

 

 

 

25

I/O

I/O

10

 

 

 

 

 

 

 

 

 

24

GND

I/O

11

 

 

 

 

 

 

 

 

 

23

I/O

 

12

13

14

15

16

17

18

19

20

21

22

 

 

I/O

I/O

I/O

I/O

GND

VCC

I/O

I/O

I/O

I/O

I/O

 

Description

The ATF1502AS is a high performance, high density Complex Programmable Logic Device (CPLD) which utilizes Atmel’s proven electrically erasable technology. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI,MSI, LSI and classic PLDs. The ATF1502AS’s enhanced routing switch matrices increase usable gate count, and the odds of successful pinlocked design modifications.

44-Lead PLCC

Top View

 

I/O

I/O

I/O/PD1

VCC/PD2

GCK2/OE2/I

GCLR/I

OE1/I

GCK1/I

GND

I/O/GCLK3

I/O

 

TDI/I/O

6

5

4

3

2

1

44

43

42

41

40

I/O

7

 

 

 

 

 

 

 

 

 

39

I/O

8

 

 

 

 

 

 

 

 

 

38

I/O/TDO

I/O

9

 

 

 

 

 

 

 

 

 

37

I/O

GND

10

 

 

 

 

 

 

 

 

 

36

I/O

PD1/I/O

11

 

 

 

 

 

 

 

 

 

35

VCC

I/O

12

 

 

 

 

 

 

 

 

 

34

I/O

I/O/TMS

13

 

 

 

 

 

 

 

 

 

33

I/O

I/O

14

 

 

 

 

 

 

 

 

 

32

I/O/TCK

VCC

15

 

 

 

 

 

 

 

 

 

31

I/O

I/O

16

 

 

 

 

 

 

 

 

 

30

GND

I/O

17

19

20

21

22

23

24

25

26

27

29

I/O

 

18

28

 

 

I/O

I/O

I/O

I/O

GND

VCC

I/O

PD2/I/O

I/O

I/O

I/O

 

The ATF1502AS has up to 32 bi-directional I/O pins and 4 dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal; register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Block Diagram

B

32

Each of the 32 macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also

feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus.

2

ATF1502AS

 

 

 

ATF1502AS

Each macrocell also generates a foldback logic term, which goes to a regional bus. Cascade logic between macrocells in the ATF1502AS allows fast, efficient generation of complex logic functions. The ATF1502AS contains four such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms.

The ATF1502AS macrocell shown in Figure 1, is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip-flop; output select and enable; and logic array inputs.

Unused product terms are automatically disabled by the compiler to decrease power consumption. A Security Fuse,

Figure 1. ATF1502AS Macrocell

when pr ogrammed, protects the contents of the ATF1502AS. Two bytes (16-bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the Security Fuse.

The ATF1502AS device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary Scan Description Language (BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

Product Terms and Select MUX

Each ATF1502AS macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1502AS’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a 5- input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as

many as 40 product terms with a very small additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selection. For registered functions, the fixed levels allow DeMorgan minimization of product terms. The XOR gate is also used to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1502AS’s flip flop has very flexible data and control functions. The data input can come from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output

3

macrocell. (This feature is automatically implemented by the fitter software). In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low.

The clock itself can either be one of the Global CLK Signal GCK[0 : 2] or an individual product term. The flip flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock enable. When the clock enable function is active and the enable signal (product term) is low, all clock edges are ignored. The flip flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product term or always off.

Output Select and Enable

The ATF1502AS macrocell output can be selected as registered or combinatorial. The buried feedback signal can be either combinatorial or registered signal regardless of whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output enable signals. Any buffer can be permanently enabled for simple output operation. Buffers can also be permanently disabled to allow use of the pin as an input. In this configuration all the macrocell resources are still available, including the buried feedback, expander and CASCADE logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well as the buried feedback signal from all 32 macrocells. The Switch Matrix in each Logic Block receives as its inputs all signals from the global bus. Under software control, up to 40 of these signals can be selected as inputs to the Logic Block.

Foldback Bus

Each macrocell also generates a foldback product term. This signal goes to the regional bus and is available to 4 macrocells. The foldback is an inverse polarity of one of the macrocell’s product terms. The 4 foldback terms in each region allows generation of high fan-in sum terms (up to 9 product terms) with a small additional delay.

Programmable Pin-Keeper Option for Inputs and I/Os

The ATF1502AS offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level.

This circuitry prevents unused input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

Input Diagram

I/O Diagram

Speed/Power Management

The ATF1502AS has several built-in speed and power management features. The ATF1502AS contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 50 MHz. This feature may be selected as a design option.

To further reduce power, each ATF1502AS macrocell has a Reduced Power bit feature. This feature allows individual macrocells to be configured for maximum power savings. This feature may be selected as a design option.

The ATF1502ASs also has an optional power down mode. In this mode, current drops to below 10 mA. When the power down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The power down

4

ATF1502AS

 

 

 

option is selected in the design source file. When enabled, the device goes into power down when either PD1 or PD2 is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s macrocell may still be used to generate buried foldback and cascade logic signals.

All Power-Down AC Characteristic parameters are computed from external input or I/O pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode (Reduced power bit turned on), the reduced power adder, tRPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.

The ATF1502AS macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power down option, macrocells that are not used in an application can be turned down thereby reducing the overall power consumption of the device.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

Design Software Support

ATF1502AS designs are supported by several third party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.

Power Up Reset

The ATF1502AS has a power-up reset option at two different voltage trip levels when the device is being powered down. Within the fitter, or during a conversion, if the “power-reset” option is turned “on” (which is the default option), the trip levels during power up or power down is at 2.8V. The user can change this default option from “on” to “off” (within the fitter or specify it as a switch during conversion). When this is done, the voltage trip level during power-down changes from 2.8V to 0.7V. This is to ensure a robust operating environment.

The registers in the ATF1502AS are designed to reset during power up. At a point delayed slightly from VCC crossing Vrst, all registers will be reset to the low state. The output state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the uncertainty of how VCC actually rises in the system, the following conditions are required:

ATF1502AS

1.The VCC rise must be monotonic,

2.After reset occurs, all input and feedback setup times must be met before driving the clock pinhigh, and,

3.The clock must remain stable during TD.

Security Fuse Usage

A single fuse is provided to prevent unauthorized copying of the ATF1502AS fuse patterns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature remains accessible.

Programming

ATF1502AS devices are In-System Programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for program and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and software to allow programming of the ATF1502AS via the PC. ISP is performed by using either a download cable, or a comparable board tester or a simple microprocessor interface.

When using the ISP hardware or S/W to program the ATF1502AS devices, four I/0 pins must be reserved for the JTAG interface. However, the logic features the macrocells associated with these I/0 pins are still available to the design for burned logic functions.

To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial Vector Format (SVF) files can be created by Atmel provided Software utilities.

ATF1502AS devices can also be programmed using standard 3rd party programmers. With 3rd party programmer the JTAG ISP port can be disabled thereby allowing 4 additional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD applications for details.

ISP Programming Protection

The ATF1502AS has a special feature which locks the device and prevents the inputs and I/O from driving if the programming process is interrupted due to any reason. The inputs and I/O default to high-Z state during such a condition. In addition, the pin keeper option preserves the previous state of the input and I/0 PMS during programming.

All ATF1502AS devices are initially shipped in the erased state thereby making them ready to use for ISP.

Note: For more information refer to the “Designing for In-Sys- tem Programmability with Atmel CPLDs” application note.

5

JTAG-BST/ISP Overview

The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1502AS. The boundary-scan technique involves the inclusion of a shiftregister stage (contained in a boundary-scan cell) adjacent to each component so that signals at component boundaries can be controlled and observed using scan testing methods. Each input pin and I/O pin has its own boundary scan cell (BSC) to support boundary scan testing. The ATF1502AS does not include a Test Reset (TRST) input pin because the TAP controller is automatically reset at power up. The five JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE and HIGHZ. The ATF1502AS’s ISP can be fully described using JTAG’s BSDL as described in IEEE Standard 1149.1b. This allows ATF1502AS programming to be described and implemented using any one of the 3rd party development tools supporting this standard.

The ATF1502AS has the option of using four JTAG-stan- dard I/O pins for boundary scan testing (BST) and in-sys- tem programming (ISP) purposes. The ATF1502AS is programmable through the four JTAG pins using the IEEE standard JTAG programming protocol established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the ISP interface for in-system programming. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O pins.

JTAG Boundary Scan Cell (BSC)

Testing

The ATF1502AS contains up to 32 I/O pins and 4 input pins, depending on the and package type selected. Each input pin and I/O pin has its own boundary scan cell (BSC) in order to support boundary scan testing as described in detail by IEEE Standard 1149.1. Typical BSC consists of three capture registers or scan registers and up to two update registers. There are two types of BSCs, one for input or I/O pin, and one for the macrocells. The BSCs in the device are chained together through the capture registers. Input to the capture register chain is fed in from the TDI pin while the output is directed to the TDO pin. Capture registers are used to capture active device data signals, to shift data in and out of the device and to load data into the update registers. Control signals are generated internally by the JTAG TAP controller. The BSC configuration for the input and I/O pins and macrocells are shown below.

BSC Configuration for Input and I/O Pins (except JTAG TAP Pins)

Note: The ATF1502AS has pull-up option on TMS and TDI pins. This feature is selected as a design option.

DC and AC Operating Conditions

 

Commercial

Industrial

 

 

 

Operating Temperature (Case)

0°C - 70°C

-40°C - 85°C

 

 

 

VCCINT or VCCIO (5V) Power

5V ± 5%

5V ± 10%

Supply

 

 

 

 

 

VCCIO (3.3V) Power Supply

3.0V - 3.6V

3.0V - 3.6V

 

 

 

6

ATF1502AS

 

 

 

Loading...
+ 12 hidden pages