ATMEL ATF1500ABV-12JC, ATF1500ABV-12AC, ATF1500ABVL-25JC, ATF1500ABVL-25AC, ATF1500ABV-15JI Datasheet

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Features

Operates Between 2.7V to 5.5V

High Density, High-Performance Electrically Erasable Complex Programmable Logic Device

44-Pin, 32 I/O CPLD

12 ns Maximum Pin-to-Pin Delay

Registered Operation Up To 90.9 MHz

Fully Connected Input and Feedback Logic Array

Flexible Logic Macrocell

D/T/Latch Configurable Flip Flops

Global and Individual Register Control Signals

Global and Individual Output Enable

Programmable Output Slew Rate

Advanced Power Management Features

Automatic 3 mA Stand-By (ATF1500ABVL)

Pin-Controlled 5 μA Stand-By Mode (Typical)

Programmable Pin-Keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

Available in 44-Pin PLCC and TQFP Packages

Advanced Flash Technology

100% Tested

Completely Reprogrammable

100 Program/Erase Cycles

20 Year Data Retention

2000V ESD Protection

200 mA Latch-Up Immunity

Supported By Popular 3rd Party Tools

Security Fuse Feature

Description

The ATF1500ABV is a high performance, high density Complex PLD. Built on an advanced Flash technology, it has maximum pin to pin delays of 12 ns and supports sequential logic operation at speeds up to 90.9 MHz. With 32 logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI, MSI and classic PLDs. The ATF1500ABV’s global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(continued)

Pin Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC

 

 

 

 

 

 

 

 

TQFP

 

 

 

 

 

 

 

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

Function

 

 

 

 

 

 

 

 

 

 

Top View

 

 

 

 

 

 

Top View

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

 

 

 

 

 

 

 

 

 

 

 

I

Logic Inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I N D E X

 

O O DP/O CC I/2E RLC/ I/1E I/KL DN O O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C O R N E R

I/ I/ I/ V O G O C G I/ I/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O

Bidirectional

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 4

4 2

4 0

3 8

3 6

3 4

 

 

Buffers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 3

 

 

4 1

 

3 9

 

3 7

 

3 5

 

 

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

I / O

GCLR

Register Reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 1

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(active low)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G N D

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 0

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 9

 

V C C

OE1,

Output Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 8

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 7

 

I / O

OE2

(active low)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 6

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

V C C

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 5

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

1 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 4

 

G N D

VCC

(+3V to 5.25V)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I / O

 

1 1

 

 

 

 

 

 

 

1 5

 

 

 

 

 

 

 

 

 

2 3

 

I / O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 3

 

 

 

1 7

 

1 9

 

2 1

 

 

 

 

Supply

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 2 1 4

1 6 1 8 2 0 2 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

 

 

PD

Power Down

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(active high)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

High-

Performance

EE PLD

ATF1500ABV

ATF1500ABVL

ATF1500ABV/L

Rev. 0723D–6/98

1

ATMEL ATF1500ABV-12JC, ATF1500ABV-12AC, ATF1500ABVL-25JC, ATF1500ABVL-25AC, ATF1500ABV-15JI Datasheet

Functional Logic Diagram(1)

Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.

2 ATF1500ABV/L

ATF1500ABV/L

The ATF1500ABV has 32 bi-directional I/O pins and 4 dedicated input pins. Each dedicated input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Each of the 32 logic macrocells generates a buried feedback, which goes to the global bus. Each input and I/O pin also feeds into the global bus. Because of this global bussing, each of these signals is always available to all 32 macrocells in the device.

Each macrocell also generates a foldback logic term, which goes to a regional bus. All signals within a regional bus are connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of complex logic functions. The ATF1500ABV contains 4 such logic chains, each capable of creating sum term logic with a fan in of up to 40 product terms.

Bus Friendly Pin-Keeper Input and

I/O’S

All Input and I/O pins on the ATF1500ABV have programmable “data keeper” circuits. If activated, when any pin is driven high or low and then subsequently left floating, it will stay at that previous high or low level.

This circuitry prevents unused Input and I/O lines from floating to intermediate voltage levels, which cause unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

Pin-keeper circuits can be disabled. Programming is controlled in the logic design file. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.

Speed/Power Management

The ATF1500ABV has several built-in speed and power management features. The ATF1500ABV contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides a proportional power savings for most applications running at system speeds below 10 MHz.

All ATF1500ABVs also have an optional pin-controlled power down mode. In this mode, current drops to below 10 μA. When the power down option is selected, the PD pin is used to power down the part. The power down option is selected in the design source file. When enabled, the device goes into power down when the PD pin is high. In the power down mode, all internal logic signals are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD is brought low. When the power down feature is enabled, the PD cannot be used as a logic input or output. However, the PD pin's macrocell may still be used to generate buried foldback and cascade logic signals.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

Design Software Support

ATF1500ABV designs are supported by several 3rd party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.

Input Diagram

 

 

I/O Diagram

 

 

 

VCC

 

VCC

 

 

 

 

 

 

 

 

 

OE

 

 

DATA

I/O

INPUT

 

 

 

100K

VCC

 

 

ESD

 

 

PROTECTION

 

 

CIRCUIT

PROGRAMMABLE

 

 

 

 

OPTION

 

 

 

100K

 

 

PROGRAMMABLE

 

 

OPTION

3

ATF1500ABV Macrocell

ATF1500ABV Macrocell

The ATF1500ABV macrocell is flexible enough to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs.

Product Terms and Select Mux

Each ATF1500ABV macrocell has five product terms. Each product term receives as its inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1500ABV macrocell's OR/XOR/CASCADE logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the OR gate, creating a five input AND/OR sum

term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay.

The macrocell's XOR gate allows efficient implementation of compare and arithmetic functions. One input to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows output polarity selection. For registered functions, the fixed levels allow De Morgan minimization of the product terms. The XOR gate is also used to emulate JK type flip flops.

Flip Flop

The ATF1500ABV’s flip flop has very flexible data and control functions. The data input can come from either the XOR gate or from a separate product term. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell.

In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode,

4 ATF1500ABV/L

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