Features
•Low Voltage and Standard Voltage Operation
–5.0 (V CC = 4.5V to 5.5V)
–2.7 (V CC = 2.7V to 5.5V)
–2.5 (V CC = 2.5V to 5.5V)
–1.8 (V CC = 1.8V to 5.5V)
•User Selectable Internal Organization
–1K: 128 x 8 or 64 x 16
–2K: 256 x 8 or 128 x 16
–4K: 512 x 8 or 256 x 16
•3-Wire Serial Interface
•2 MHz Clock Rate (5V) Compatibility
•Self-Timed Write Cycle (10 ms max)
•High Reliability
–Endurance: 1 Million Write Cycles
–Data Retention: 100 Years
–ESD Protection: >4000V
•Automotive Grade and Extended Temperature Devices Available
•8-Pin PDIP, 8-Pin JEDEC and EIAJ SOIC, and 8-Pin TSSOP Packages
Description
The AT93C46/56/57/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64/128/256 words of 16 bits each, when the ORG Pin is connected to VCC and 128/256/512 words of 8 bits each when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. The AT93C46/56/57/66 is available in space saving 8-pin PDIP and 8-pin JEDEC and EIAJ SOIC packages.
Pin Configurations
Pin Name |
Function |
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CS |
Chip Select |
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SK |
Serial Data Clock |
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DI |
Serial Data Input |
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DO |
Serial Data Output |
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GND |
Ground |
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VCC |
Power Supply |
ORG |
Internal Organization |
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DC |
Don’t Connect |
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8-Pin SOIC
Rotated (R)
(1K JEDEC Only)
(continued)
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8-Pin PDIP |
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CS |
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1 |
8 |
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VCC |
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SK |
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2 |
7 |
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DC |
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DI |
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3 |
6 |
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ORG |
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DO |
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4 |
5 |
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GND |
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8-Pin SOIC |
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CS |
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1 |
8 |
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VCC |
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SK |
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2 |
7 |
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DC |
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DI |
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3 |
6 |
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ORG |
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DO |
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4 |
5 |
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GND |
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8-Pin TSSOP |
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DC |
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1 |
8 |
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ORG |
CS |
1 |
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8 |
VCC |
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VCC |
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2 |
7 |
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GND |
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CS |
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3 |
6 |
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DO |
SK |
2 |
7 |
DC |
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SK |
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4 |
5 |
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DI |
DI |
3 |
6 |
ORG |
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DO |
4 |
5 |
GND |
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3-Wire Serial |
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EEPROMs |
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1K |
(128 x 8 or 64 x 16) |
2K |
(256 x 8 or 128 x 16) |
4K |
(512 x 8 or 256 x 16) |
AT93C46 |
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AT93C56 |
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AT93C57 |
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AT93C66 |
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Rev. 0172K–07/98 |
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1 |
The AT93C46/56/57/66 is enabled through the Chip Select pin (CS), and accessed via a 3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a READ instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The WRITE cycle is completely self-timed and no separate ERASE cycle is required before WRITE. The WRITE cycle is only enabled when the part is in the
Absolute Maximum Ratings*
..................................Operating Temperature |
-55°C to +125°C |
Storage Temperature ..................................... |
-65°C to +150°C |
Voltage on Any Pin |
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with Respect to Ground ..................................... |
-1.0V to +7.0V |
Maximum Operating Voltage........................................... |
6.25V |
DC Output Current........................................................ |
5.0 mA |
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Block Diagram
ERASE/WRITE ENABLE state. When CS is brought “high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY status of the part.
The AT93C46 is available in 4.5V to 5.5V, 2.7V to 5.5V, 2 . 5 V t o 5 . 5 V , a n d 1 . 8 V t o 5 . 5 V v e r s i o n s . T h e AT93C56/57/66 is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions.
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Note: 1. When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device (of approximately 1 MΩ) will select the x 16 organization. This feature is not available on 1.8V devices.
2 AT93C46/56/57/66
AT93C46/56/57/66
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
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Test Conditions |
Max |
Units |
Conditions |
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COUT |
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Output Capacitance (DO) |
5 |
pF |
VOUT = 0V |
CIN |
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Input Capacitance (CS, SK, DI) |
5 |
pF |
VIN = 0V |
Note: |
1. This parameter is characterized and is not 100% tested. |
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DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol |
Parameter |
Test Condition |
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Min |
Typ |
Max |
Unit |
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VCC1 |
Supply Voltage |
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1.8 |
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5.5 |
V |
VCC2 |
Supply Voltage |
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2.5 |
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5.5 |
V |
VCC3 |
Supply Voltage |
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2.7 |
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5.5 |
V |
VCC4 |
Supply Voltage |
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4.5 |
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5.5 |
V |
ICC |
Supply Current |
VCC = 5.0V |
READ at 1.0 MHz |
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0.5 |
2.0 |
mA |
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WRITE at 1.0 MHz |
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0.5 |
2.0 |
mA |
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ISB1 |
Standby Current |
VCC = 1.8V |
CS = 0V |
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0 |
0.1 |
μA |
ISB2 |
Standby Current |
VCC = 2.5V |
CS = 0V |
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6.0 |
10.0 |
μA |
ISB3 |
Standby Current |
VCC = 2.7V |
CS = 0V |
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6.0 |
10.0 |
μA |
ISB4 |
Standby Current |
VCC = 5.0V |
CS = 0V |
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17 |
30 |
μA |
IIL |
Input Leakage |
VIN = 0V to VCC |
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0.1 |
1.0 |
μA |
IOL |
Output Leakage |
VIN = 0V to VCC |
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0.1 |
1.0 |
μA |
(1) |
Input Low Voltage |
4.5V ≤ VCC ≤ 5.5V |
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-0.6 |
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0.8 |
V |
VIL1 |
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(1) |
Input High Voltage |
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2.0 |
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VCC + 1 |
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VIH1 |
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(1) |
Input Low Voltage |
1.8V ≤ VCC ≤ 2.7V |
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-0.6 |
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VCC x 0.3 |
V |
VIL2 |
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(1) |
Input High Voltage |
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VCC x 0.7 |
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VCC + 1 |
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VIH2 |
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VOL1 |
Output Low Voltage |
4.5V ≤ VCC ≤ 5.5V |
IOL = 2.1 mA |
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0.4 |
V |
VOH1 |
Output High Voltage |
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IOH = -0.4 mA |
2.4 |
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V |
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VOL2 |
Output Low Voltage |
1.8V ≤ VCC ≤ 2.7V |
IOL = 0.15 mA |
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0.2 |
V |
VOH2 |
Output High Voltage |
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IOH = -100 μA |
VCC - 0.2 |
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V |
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Note: 1. |
VIL min and VIH max are reference only and are not tested. |
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3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, V CC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol |
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Parameter |
Test Condition |
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Min |
Typ |
Max |
Units |
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4.5V ≤ VCC ≤ 5.5V |
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0 |
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2 |
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fSK |
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SK Clock Frequency |
2.7V ≤ VCC ≤ 5.5V |
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0 |
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1 |
MHz |
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2.5V ≤ VCC ≤ 5.5V |
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0 |
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0.5 |
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1.8V ≤ VCC ≤ 5.5V |
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0 |
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0.25 |
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4.5V ≤ VCC |
≤ 5.5V |
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250 |
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tSKH |
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SK High Time |
2.7V ≤ VCC |
≤ 5.5V |
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250 |
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ns |
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2.5V ≤ VCC ≤ 5.5V |
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500 |
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1.8V ≤ VCC ≤ 5.5V |
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1000 |
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4.5V ≤ VCC ≤ 5.5V |
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250 |
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tSKL |
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SK Low Time |
2.7V ≤ VCC ≤ 5.5V |
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250 |
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ns |
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2.5V ≤ VCC |
≤ 5.5V |
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500 |
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1.8V ≤ VCC |
≤ 5.5V |
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1000 |
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4.5V ≤ VCC ≤ 5.5V |
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250 |
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tCS |
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Minimum CS |
2.7V ≤ VCC ≤ 5.5V |
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250 |
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ns |
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Low Time |
2.5V ≤ VCC ≤ 5.5V |
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500 |
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1.8V ≤ VCC ≤ 5.5V |
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1000 |
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4.5V |
≤ VCC |
≤ 5.5V |
50 |
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tCSS |
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CS Setup Time |
Relative to SK |
2.7V |
≤ VCC |
≤ 5.5V |
50 |
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ns |
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2.5V |
≤ VCC |
≤ 5.5V |
100 |
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1.8V |
≤ VCC ≤ 5.5V |
200 |
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4.5V |
≤ VCC ≤ 5.5V |
100 |
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tDIS |
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DI Setup Time |
Relative to SK |
2.7V |
≤ VCC ≤ 5.5V |
100 |
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ns |
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2.5V |
≤ VCC |
≤ 5.5V |
200 |
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1.8V |
≤ VCC |
≤ 5.5V |
400 |
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tCSH |
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CS Hold Time |
Relative to SK |
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0 |
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ns |
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4.5V |
≤ VCC |
≤ 5.5V |
100 |
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tDIH |
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DI Hold Time |
Relative to SK |
2.7V |
≤ VCC |
≤ 5.5V |
100 |
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ns |
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2.5V |
≤ VCC |
≤ 5.5V |
200 |
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1.8V |
≤ VCC ≤ 5.5V |
400 |
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4.5V |
≤ VCC ≤ 5.5V |
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250 |
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tPD1 |
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Output Delay to ‘1’ |
AC Test |
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2.7V |
≤ VCC ≤ 5.5V |
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250 |
ns |
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2.5V |
≤ VCC |
≤ 5.5V |
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500 |
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1.8V |
≤ VCC |
≤ 5.5V |
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1000 |
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4.5V |
≤ VCC ≤ 5.5V |
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250 |
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tPD0 |
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Output Delay to ‘0’ |
AC Test |
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2.7V |
≤ VCC ≤ 5.5V |
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250 |
ns |
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2.5V |
≤ VCC |
≤ 5.5V |
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500 |
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1.8V |
≤ VCC ≤ 5.5V |
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1000 |
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4.5V |
≤ VCC |
≤ 5.5V |
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250 |
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tSV |
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CS to Status Valid |
AC Test |
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2.7V |
≤ VCC |
≤ 5.5V |
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250 |
ns |
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2.5V |
≤ VCC |
≤ 5.5V |
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500 |
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1.8V |
≤ VCC ≤ 5.5V |
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1000 |
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4.5V |
≤ VCC ≤ 5.5V |
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100 |
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tDF |
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CS to DO in High |
AC Test |
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2.7V ≤ VCC ≤ 5.5V |
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100 |
ns |
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Impedance |
CS = VIL |
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2.5V ≤ VCC |
≤ 5.5V |
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200 |
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1.8V ≤ VCC ≤ 5.5V |
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400 |
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tWP |
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Write Cycle Time |
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0.1 |
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10 |
ms |
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4.5V |
≤ VCC |
≤ 5.5V |
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1 |
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ms |
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Endurance(1) |
5.0V, 25°C, Page Mode |
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1M |
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Write Cycles |
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Note: |
1. This parameter is characterized and is not 100% tested. |
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4 AT93C46/56/57/66
AT93C46/56/57/66
Instruction Set for the AT93C46
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Op |
Address |
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Data |
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Instruction |
SB |
Code |
x 8 |
x 16 |
x 8 |
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x 16 |
Comments |
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READ |
1 |
10 |
A6 - A0 |
A5 - A0 |
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Reads data stored in memory, at |
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specified address. |
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EWEN |
1 |
00 |
11XXXXX |
11XXXX |
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Write enable must precede all |
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programming modes. |
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ERASE |
1 |
11 |
A6 - A0 |
A5 - A0 |
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Erase memory location An - A0. |
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WRITE |
1 |
01 |
A6 - A0 |
A5 - A0 |
D7 - D0 |
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D15 - D0 |
Writes memory location An - A0. |
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ERAL |
1 |
00 |
10XXXXX |
10XXXX |
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Erases all memory locations. Valid |
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only at VCC = 4.5V to 5.5V. |
WRAL |
1 |
00 |
01XXXXX |
01XXXX |
D7 - D0 |
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D15 - D0 |
Writes all memory locations. Valid |
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only at VCC = 4.5V to 5.5V. |
EWDS |
1 |
00 |
00XXXXX |
00XXXX |
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Disables all programming instructions. |
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Instruction Set for the AT93C57
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Op |
Address |
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Data |
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Instruction |
SB |
Code |
x 8 |
x 16 |
x 8 |
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x 16 |
Comments |
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READ |
1 |
10 |
A7 - A0 |
A6 - A0 |
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Reads data stored in memory, at |
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specified address. |
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EWEN |
1 |
00 |
11XXXXXX |
11XXXXX |
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Write enable must precede all |
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programming modes. |
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ERASE |
1 |
11 |
A7 - A0 |
A6 - A0 |
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Erase memory location An - A0. |
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WRITE |
1 |
01 |
A7 - A0 |
A6 - A0 |
D7 - D0 |
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D15 - D0 |
Writes memory location An - A0. |
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ERAL |
1 |
00 |
10XXXXXX |
10XXXXX |
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Erases all memory locations. Valid |
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only at VCC = 4.5V to 5.5V. |
WRAL |
1 |
00 |
01XXXXXX |
01XXXXX |
D7 - D0 |
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D15 - D0 |
Writes all memory locations. Valid |
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only at VCC = 4.5V to 5.5V. |
EWDS |
1 |
00 |
00XXXXXX |
00XXXXX |
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Disables all programming instructions. |
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5