ATMEL AT90S8515-8JI, AT90S8515-8JC, AT90S8515-8AI, AT90S8515-4PI, AT90S8515-4PC Datasheet

Features

•AVR - High Performance and Low Power RISC Architecture

•118 Powerful Instructions - Most Single Clock Cycle Execution

•8K bytes of In-System Reprogrammable Flash

–SPI Serial Interface for Program Downloading

–Endurance: 1,000 Write/Erase Cycles

•512 bytes EEPROM

–Endurance: 100,000 Write/Erase Cycles

•512 bytes Internal SRAM

•32 x 8 General Purpose Working Registers

•32 Programmable I/O Lines

•Programmable Serial UART

•SPI Serial Interface

•VCC: 2.7 - 6.0V

•Fully Static Operation

–0 - 8 MHz 4.0 - 6.0V,

–0 - 4 MHz 2.7 - 4.0V

•Up to 8 MIPS Throughput at 8 MHz

•One 8-Bit Timer/Counter with Separate Prescaler

•One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes

•Dual PWM

•External and Internal Interrupt Sources

•Programmable Watchdog Timer with On-Chip Oscillator

•On-Chip Analog Comparator

•Low Power Idle and Power Down Modes

•Programming Lock for Software Security

Description

The AT90S8515 is a low-power CMOS 8-bit microcontroller based on the AVR ® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

(continued)

Pin Configurations

8-Bit

Microcontroller

with 8K bytes

In-System

Programmable

Flash

AT90S8515

Preliminary

Rev. 0841D–06/98

1

Block Diagram

Figure 1. The AT90S8515 Block Diagram

The AT90S8515 provides the following features: 8K bytes of In-System Programmable Flash, 512 bytes EEPROM, 512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, flexible timer/counters with compare modes, internal and external interrupts, a programmable serial UART, programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

The device is manufactured using Atmel’s high density non-volatile memory technology. The on-chip in-system programmable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90S8515 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, incircuit emulators, and evaluation kits.

2	AT90S8515

Pin Descriptions

VCC

Supply voltage

GND

Ground

Port A (PA7..PA0)

Port A is an 8-bit bidirectional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated.

Port A serves as Multiplexed Address/Data input/output when using external SRAM.

Port B (PB7..PB0)

Port B is an 8-bit bidirectional I/O pins with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated.

Port B also serves the functions of various special features of the AT90S8515 as listed on page 46.

Port C (PC7..PC0)

Port C is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated.

Port C also serves as Address output when using external SRAM.

Port D (PD7..PD0)

Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated.

Port D also serves the functions of various special features of the AT90S8515 as listed on page 52.

RESET

Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier

ICP

ICP is the input pin for the Timer/Counter1 Input Capture function.

OC1B

OC1B is the output pin for the Timer/Counter1 Output CompareB function

AT90S8515

ALE

ALE is the Address Latch Enable used when the External Memory is enabled. The ALE strobe is used to latch the low-order address (8 bits) into an address latch during the first access cycle, and the AD0-7 pins are used for data during the second access cycle.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

Figure 2. Oscillator Connections

Figure 3. External Clock Drive Configuration

3

AT90S8515 Architectural Overview

The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle.

Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.

Figure 4. The AT90S8515 AVR Enhanced RISC Architecture

The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S8515 AVR Enhanced RISC microcontroller architecture.

In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing them to be accessed as though they were ordinary memory locations.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F.

The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system programmable Flash memory.

With the relative jump and call instructions, the whole 4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initial-

4	AT90S8515

AT90S8515

ize the SP in the reset routine (before subroutines or inter- Figure 5. Memory Maps rupts are executed). The 16-bit stack pointer SP is read/write accessible in the I/O space.

The 512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt vector address the higher the priority.

The General Purpose Register File

Figure 6 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6. AVR CPU General Purpose Working Registers

	7	0	Addr.
	R0		$00
	R1		$01
	R2		$02
	…
	R13		$0D
General	R14		$0E
Purpose	R15		$0F
Working	R16		$10
Registers	R17		$11
	…
	R26		$1A	X-register low byte
	R27		$1B	X-register high byte
	R28		$1C	Y-register low byte
	R29		$1D	Y-register high byte
	R30		$1E	Z-register low byte
	R31		$1F	Z-register high byte

All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND and OR and all other

operations between two registers or on a single register apply to the entire register file.

As shown in Figure 6, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X,Y and Z registers can be set to index any register in the file.

5

The X-Register, Y-Register And Z-Register

The registers R26..R31 have some added functions to their general purpose usage. These registers are address point-

Figure 7. The X, Y and Z Registers

ers for indirect addressing of the Data Space. The three indirect address registers X, Y and Z are defined as:

	15			0
X - register	7	0	7	0
		R27 ($1B)		R26 ($1A)
	15			0
Y - register	7	0	7	0
		R29 ($1D)		R28 ($1C)
	15			0
Z - register	7	0	7	0
		R31 ($1F)		R30 ($1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment and decrement (see the descriptions for the different instructions).

The ALU - Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logical and bit-functions.

The In-System Programmable Flash Program Memory

The AT90S8515 contains 8K bytes on-chip In-System Programmable Flash memory for program storage. Since all

instructions are 16-or 32-bit words, the Flash is organized as 4K x 16. The Flash memory has an endurance of at least 1000 write/erase cycles. The AT90S8515 Program Counter (PC) is 12 bits wide, thus addressing the 4096 program memory addresses.

See page 62 for a detailed description on Flash data downloading.

Constant tables must be allocated within the address 0-4K (see the LPM - Load Program Memory instruction description).

See page 8 for the different program memory addressing modes.

6	AT90S8515

				AT90S8515
The SRAM Data Memory - Internal and External
The following figure shows how the AT90S8515 SRAM
Memory is organized:
Figure 8. SRAM Organization
	Register File		Data Address Space
	R0		$0000
	R1		$0001
	R2		$0002
	¼		¼
	R29		$001D
	R30		$001E
	R31		$001F
	I/O Registers
	$00		$0020
	$01		$0021
	$02		$0022
	…		…
	$3D		$005D
	$3E		$005E
	$3F		$005F
			Internal SRAM
			$0060
			$0061
			¼
			$025E
			$025F
			External SRAM
			$0260
			$0261
			…
			$FFFE
			$FFFF

The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The first 96 locations address the Register File + I/O Memory, and the next 512 locations address the internal data SRAM. An optional external data SRAM can be placed in the same SRAM memory space. This SRAM will occupy the location following the internal SRAM and up to as much as 64K - 1, depending on SRAM size.

When the addresses accessing the data memory space exceeds the internal data SRAM locations, the external data SRAM is accessed using the same instructions as for the internal data SRAM access. When the internal data space is accessed, the read and write strobe pins (RD and WR) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR register. See page 21 for details.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, PUSH and POP take one additional clock cycle. If the stack is placed in external SRAM, interrupts, subroutine calls and returns take two clock cycles extra because the two-byte program counter is pushed and popped. When external SRAM interface is used with wait state, two additional clock cycles is used per byte. This has the following effect: Data transfer instructions take two extra clock cycles, whereas interrupt, subroutine calls and returns will need four clock cycles more than specified in the instruction set manual.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-Decrement and Indirect with Post-Increment. In the register file, registers R26 to R31 feature the indirect addressing pointer registers.

7

The direct addressing reaches the entire data space.

The Indirect with Displacement mode features a 63 address locations reach from the base address given by the Y or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y and Z are decremented and incremented.

The 32 general purpose working registers, 64 I/O registers, the 512 bytes of internal data SRAM, and the 64K bytes of optional external data SRAM in the AT90S8515 are all accessible through all these addressing modes.

See the next section for a detailed description of the different addressing modes.

The Program and Data Addressing Modes

The AT90S8515 AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the program memory (Flash) and data memory (SRAM, Register File and I/O Memory). This section describes the different addressing modes supported by the AVR architecture. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single Register RD

Figure 9. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers RD AND RR

Figure 10. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

I/O Direct

Figure 11. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.

Data Direct

Figure 12. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a twoword instruction. Rd/Rr specify the destination or source register.

Data Indirect With Displacement

Figure 13. Data Indirect with Displacement

Operand address is the result of the Y or Z-register contents added to the address contained in 6 bits of the instruction word.

8	AT90S8515

Data Indirect

Figure 14. Data Indirect Addressing

Operand address is the contents of the X, Y or the Z-regis- ter.

Data Indirect With Pre-Decrement

Figure 15. Data Indirect Addressing With Pre-Decrement

The X, Y or the Z-register is decremented before the operation. Operand address is the decremented contents of the X, Y or the Z-register.

Data Indirect With Post-Increment

Figure 16. Data Indirect Addressing With Post-Increment

The X, Y or the Z-register is incremented after the operation. Operand address is the content of the X, Y or the Z- register prior to incrementing.

AT90S8515

Constant Addressing Using The LPM Instruction

Figure 17. Code Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 4K) and LSB, select low byte if cleared (LSB = 0) or high byte if set (LSB = 1).

Indirect Program Addressing, IJMP and ICALL

Figure 18. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e. the PC is loaded with the contents of the Z- register).

Relative Program Addressing, RJMP and RCALL

Figure 19. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is -2048 to 2047.

9

The EEPROM Data Memory

The AT90S8515 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 32 specifying the EEPROM address registers, the EEPROM data register, and the EEPROM control register.

For the SPI data downloading, see page 62 for a detailed description.

Memory Access Times and Instruction Execution Timing

This section describes the general access timing concepts for instruction execution and internal memory access.

The AVR CPU is driven by the System Clock Ø, directly generated from the external clock crystal for the chip. No internal clock division is used.

Figure 20 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 20. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 21 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two reg-

ister operands is executed, and the result is stored back to the destination register.

Figure 21. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The internal data SRAM access is performed in two System Clock cycles as described in Figure 22.

10	AT90S8515

AT90S8515

Figure 22. On-Chip Data SRAM Access Cycles

T1

T2

T3

T4

System Clock Ø

Address

Prev. Address

Address

Data

WR

Data

RD

The external data SRAM access is performed in two System Clock cycles as described in Figure 22.

Figure 23. External Data SRAM Memory Cycles without Wait State

T1 T2 T3

System Clock Ø

ALE

Address [15..8]	Prev. Address		Address
Data / Address [7..0]	Prev. Address	Address	Data	Address
WR
Data / Address [7..0]	Prev. Address	Address	Data	Address
RD

Read Write

Read Write

The external data SRAM memory access cycle with the Wait State bit enabled (Wait State active) is shown in Figure 24.

Figure 24. External Data SRAM Memory Cycles with Wait State

	T1	T2	T3
System Clock Ø
ALE
Address [15..8]	Prev. Address		Address
Data / Address [7..0]	Prev. Address	Address	Data
WR
Data / Address [7..0]	Prev. Address	Address	Data

RD

T4

			Write
	Addr.
			Read
	Addr.

11

I/O Memory

The I/O space definition of the AT90S8515 is shown in the following table:

Table 1. AT90S8515 I/O Space

Address Hex		Name	Function
$3F	($5F)	SREG	Status Register
$3E	($5E)	SPH	Stack Pointer High
$3D	($5D)	SPL	Stack Pointer Low
$3B	($5B)	GIMSK	General Interrupt Mask register
$3A	($5A)	GIFR	General Interrupt Flag Register
$39 ($59)		TIMSK	Timer/Counter Interrupt Mask register
$38 ($58)		TIFR	Timer/Counter Interrupt Flag register
$35	($55)	MCUCR	MCU general Control Register
$33	($53)	TCCR0	Timer/Counter0 Control Register
$32	($52)	TCNT0	Timer/Counter0 (8-bit)
$2F	($4F)	TCCR1A	Timer/Counter1 Control Register A
$2E	($4E)	TCCR1B	Timer/Counter1 Control Register B
$2D	($4D)	TCNT1H	Timer/Counter1 High Byte
$2C	($4C)	TCNT1L	Timer/Counter1 Low Byte
$2B	($4B)	OCR1AH	Timer/Counter1 Output Compare Register A High Byte
$2A	($4A)	OCR1AL	Timer/Counter1 Output Compare Register A Low Byte
$29 ($49)		OCR1BH	Timer/Counter1 Output Compare Register B High Byte
$28 ($48)		OCR1BL	Timer/Counter1 Output Compare Register B Low Byte
$25 ($45)		ICR1H	T/C 1 Input Capture Register High Byte
$24 ($44)		ICR1L	T/C 1 Input Capture Register Low Byte
$21 ($41)		WDTCR	Watchdog Timer Control Register
$1F ($3E)		EEARH	EEPROM Address Register High Byte
$1E	($3E)	EEARL	EEPROM Address Register Low Byte
$1D	($3D)	EEDR	EEPROM Data Register
$1C	($3C)	EECR	EEPROM Control Register
$1B	($3B)	PORTA	Data Register, Port A
$1A	($3A)	DDRA	Data Direction Register, Port A
$19	($39)	PINA	Input Pins, Port A
$18	($38)	PORTB	Data Register, Port B
$17	($37)	DDRB	Data Direction Register, Port B
$16	($36)	PINB	Input Pins, Port B
$15	($35)	PORTC	Data Register, Port C
$14	($34)	DDRC	Data Direction Register, Port C
$13	($33)	PINC	Input Pins, Port C

12	AT90S8515

AT90S8515

Table 1. AT90S8515 I/O Space (Continued)

Address Hex		Name	Function
$12	($32)	PORTD	Data Register, Port D
$11	($31)	DDRD	Data Direction Register, Port D
$10	($30)	PIND	Input Pins, Port D
$0F	($2F)	SPDR	SPI I/O Data Register
$0E	($2E)	SPSR	SPI Status Register
$0D	($2D)	SPCR	SPI Control Register
$0C	($2C)	UDR	UART I/O Data Register
$0B	($2B)	USR	UART Status Register
$0A	($2A)	UCR	UART Control Register
$09	($29)	UBRR	UART Baud Rate Register
$08	($28)	ACSR	Analog Comparator Control and Status Register

Note: reserved and unused locations are not shown in the table

All the different AT90S8515 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details.

The Status Register - SREG

When using the I/O specific commands, IN, OUT,SBIS and SBIC, the I/O addresses $00 - $3F must be used. When addressing I/O registers as SRAM, $20 must be added to this address. All I/O register addresses throughout this document are shown with the SRAM address in parentheses.

The different I/O and peripherals control registers are explained in the following chapters.

The AVR status register - SREG - at I/O space location $3F ($5F) is defined as:

Bit	7	6	5	4	3	2	1	0
									SREG
$3F ($5F)	I	T	H	S	V	N	Z	C
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

• Bit 7 - I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the interrupt mask registers - GIMSK and TIMSK. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled independent of the GIMSK and TIMSK values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.

• Bit 6 - T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.

• Bit 1 - Z: Zero Flag

The zero flag Z indicates a zero result after the different

• Bit 5 - H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.

• Bit 4 - S: Sign Bit, S = N Å V

The S-bit is always an exclusive or between the negative flag N and the two’s complement overflow flag V. See the Instruction Set Description for detailed information.

• Bit 3 - V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See the Instruction Set Description for detailed information.

• Bit 2 - N: Negative Flag

The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.

arithmetic and logic operations. See the Instruction Set Description for detailed information.

13

• Bit 0 - C: Carry Flag

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.

The Stack Pointer - SP

The general AVR 16-bit Stack Pointer is effectively built up of two 8-bit registers in the I/O space locations $3E ($5E) and $3D ($5D). As the AT90S8515 supports up to 64 kB external SRAM, all 16-bits are used.

Bit		15	14	13	12	11	10	9	8
$3E ($5E)		SP15	SP14	SP13	SP12	SP11	SP10	SP9	SP8	SPH
										SPL
$3D ($5D)		SP7	SP6	SP5	SP4	SP3	SP2	SP1	SP0
		7	6	5	4	3	2	1	0
Read/Write		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
		R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value		0	0	0	0	0	0	0	0
		0	0	0	0	0	0	0	0

The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when data is pushed onto the Stack with subroutine CALL and interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt IRET.

Reset and Interrupt Handling

The AT90S8515 provides 12 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt.

The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0 etc.

14	AT90S8515

AT90S8515

Table 2. Reset and Interrupt Vectors

Vector No.	Program Address	Source	Interrupt Definition
1	$000	RESET	Hardware Pin and Watchdog Reset
2	$001	INT0	External Interrupt Request 0
3	$002	INT1	External Interrupt Request 1
4	$003	TIMER1 CAPT	Timer/Counter1 Capture Event
5	$004	TIMER1 COMPA	Timer/Counter1 Compare Match A
6	$005	TIMER1 COMPB	Timer/Counter1 Compare Match B
7	$006	TIMER1 OVF	Timer/Counter1 Overflow
8	$007	TIMER0, OVF	Timer/Counter0 Overflow
9	$008	SPI, STC	Serial Transfer Complete
10	$009	UART, RX	UART, Rx Complete
11	$00A	UART, UDRE	UART Data Register Empty
12	$00B	UART, TX	UART, Tx Complete
13	$00C	ANA_COMP	Analog Comparator

The most typical and general program setup for the Reset and Interrupt Vector Addresses are:

Address	Labels	Code		Comments
$000		rjmp	RESET	; Reset Handler
$001		rjmp	EXT_INT0	; IRQ0 Handler
$002		rjmp	EXT_INT1	; IRQ1 Handler
$003		rjmp	TIM1_CAPT	; Timer1	Capture Handler
$004		rjmp	TIM1_COMPA	; Timer1	CompareA Handler
$005		rjmp	TIM1_COMPB	; Timer1	CompareB Handler
$006		rjmp	TIM1_OVF	; Timer1	Overflow Handler
$007		rjmp	TIM0_OVF	; Timer0	Overflow Handler
$008		rjmp	SPI_STC	; SPI Transfer Complete Handler
$009		rjmp	UART_RXC	; UART RX Complete Handler
$00a		rjmp	UART_DRE	; UDR Empty Handler
$00b		rjmp	UART_TXC	; UART TX Complete Handler
$00c		rjmp	ANA_COMP	; Analog	Comparator Handler
;
$00d	MAIN:	<instr>	xxx	; Main program start
…	…	…	…

Reset Sources

The AT90S8515 has three sources of reset:

•Power-On Reset. The MCU is reset when a supply voltage is applied to the VCC and GND pins.

•External Reset. The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles.

•Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000.

The instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 25 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry.

15

Figure 25. Reset Logic

Table 3. Reset Characteristics (VCC = 5.0V)

Symbol		Parameter		Min	Typ	Max	Units
VPOT		Power-On Reset Threshold Voltage		1.8	2	2.2	V
VRST			Pin Threshold Voltage		VCC/2		V
		RESET
tPOR		Power-On Reset Period		2	3	4	ms
tTOUT		Reset Delay Time-Out Period FSTRT Unprogrammed		11	16	21	ms
tTOUT		Reset Delay Time-Out Period FSTRT Programmed		1.0	1.1	1.2	ms

Power-on Reset

A Power-On Reset (POR) circuit ensures that the device is not started until VCC has reached a safe level. As shown in Figure 25, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 26 and Figure 27). The total reset period is the Power-

On Reset period - tPOR + the Delay Time-out period - tTOUT. The FSTRT fuse bit in the Flash can be programmed to

give a shorter start-up time if a ceramic resonator or any other fast-start oscillator is used to clock the MCU.

If the build-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the pin low for a period after VCC has been applied, the Power-On Reset period can be extended. Refer to Figure 28 for a timing example on this.

Figure 26. MCU Start-Up, RESET Tied to VCC. Rapidly Rising VCC

16	AT90S8515

AT90S8515

Figure 27. MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC

Figure 28. MCU Start-Up, RESET Controlled Externally

External Reset

An external reset is generated by a low level on the RESET pin. The RESET pin must be held low for at least two crystal clock cycles. When the applied signal reaches the Reset Threshold Voltage - VRST on its positive edge, the delay

timer starts the MCU after the Time-out period tTOUT has expired.

17

Figure 29. External Reset During Operation

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this

Figure 30. Watchdog Reset During Operation

pulse, the delay timer starts counting the Time-out period

tTOUT. Refer to page 30 for details on operation of the Watchdog.

Interrupt Handling

The AT90S8515 has two 8-bit Interrupt Mask control registers; GIMSK - General Interrupt Mask register and TIMSK - Timer/Counter Interrupt Mask register.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software must set (one) the I-bit to enable interrupts.

The General Interrupt Mask Register - GIMSK

When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared.

Bit		7	6	5	4	3	2	1	0
$3B ($5B)		INT1	INT0	-	-	-	-	-	-	GIMSK
Read/Write		R/W	R/W	R	R	R	R	R	R
Initial value		0	0	0	0	0	0	0	0

• Bit 7 - INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising

or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is executed from program memory address $002. See also “External Interrupts”.

18	AT90S8515

AT90S8515

• Bit 6 - INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is con-

The General Interrupt Flag Register - GIFR

figured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from program memory address $001. See also “External Interrupts.”

• Bits 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always read as zero.

Bit	7	6	5	4	3	2	1	0
									GIFR
$3A ($5A)	INTF1	INTF0	-	-	-	-	-	-
Read/Write	R/W	R/W	R	R	R	R	R	R
Initial value	0	0	0	0	0	0	0	0

• Bit 7 - INTF1: External Interrupt Flag1

When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 6 - INTF0: External Interrupt Flag0

When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in SREG and

The Timer/counter Interrupt Mask Register - TIMSK

the INT0 bit in GIMSK are set (one), the MCU will jump to the interrupt vector at address $001. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bits 5..0 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always read as zero.

Bit	7	6	5	4	3	2	1	0
$39 ($59)	TOIE1	OCIE1A	OCIE1B	-	TICIE1	-	TOIE0	-	TIMSK
Read/Write	R/W	R/W	R/W	R	R/W	R	R/W	R
Initial value	0	0	0	0	0	0	0	0

•Bit 7 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $006) is executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer/Counter1) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR. When Timer/Counter1 is in PWM mode, the Timer Overflow flag is set when the counter changes counting direction at $0000.

•Bit 6 - OCE1A:Timer/Counter1 Output CompareA Match Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareA Match interrupt is enabled. The corresponding interrupt (at vector $004) is executed if a CompareA match in Timer/Counter1 occurs. The CompareA Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

•Bit 5 - OCIE1B:Timer/Counter1 Output CompareB Match Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 CompareB Match interrupt is enabled. The corresponding interrupt (at vector $005) is executed if a CompareB match in Timer/Counter1

occurs. The CompareB Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 4 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

•Bit 3 - TICIE1: Timer/Counter1 Input Capture Interrupt Enable

When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 Input Capture Event Interrupt is enabled. The corresponding interrupt (at vector $003) is executed if a capture-triggering event occurs on pin 31, ICP. The Input Capture Flag in Timer/Counter1 is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

• Bit 2 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 1 - TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $008) is executed if an overflow in Timer/Counter0 occurs. The

19

Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.

The Timer/Counter Interrupt Flag Register - TIFR

• Bit 0 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

Bit	7	6	5	4	3	2	1	0
$38 ($58)	TOV1	OCF1A	OCIFB	-	ICF1	-	TOV0	-	TIFR
Read/Write	R/W	R/W	R/W	R	R/W	R	R/W	R
Initial value	0	0	0	0	0	0	0	0

• Bit 7 - TOV1: Timer/Counter1 Overflow Flag

The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is cleared by writing a logic one to the flag. When the I-bit in SREG, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the Timer/Counter1 Overflow Interrupt is executed. In PWM mode, this bit is set when Timer/Counter1 changes counting direction at $0000.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1A is cleared by writing a logic one to th e f la g . W he n th e I - bi t i n S RE G , a n d O CI E 1A (Timer/Counter1 Compare match InterruptA Enable), and the OCF1A are set (one), the Timer/Counter1 Compare match Interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between the Timer/Counter1 and the data in OCR1B - Output Compare Register 1B. OCF1B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF1B is cleared by writing a logic one to the flag .. Whe n the I - b it i n S REG , an d O CIE1B (Timer/Counter1 Compare match InterruptB Enable), and the OCF1B are set (one), the Timer/Counter1 Compare match Interrupt is executed.

• Bit 4 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 3 - ICF1: - Input Capture Flag 1

The ICF1 bit is set (one) to flag an input capture event, indicating that the Timer/Counter1 value has been transferred to the input capture register - ICR1. ICF1 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ICF1 is cleared by writing a logic one to the flag.

• Bit 2 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

• Bit 1 - TOV: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.

• Bit 0 - Res: Reserved bit

This bit is a reserved bit in the AT90S8515 and always reads zero.

External Interrupts

The external interrupts are triggered by the INT1 and INT0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0/INT1 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the MCU Control Register - MCUCR. When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low.

The external interrupts are set up as described in the specification for the MCU Control Register - MCUCR.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. 4 clock cycles after the interrupt flag has been set, the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (2 bytes) is pushed onto the Stack, and the Stack Pointer is decremented by 2. The vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine (same as for a subroutine call routine) takes 4 clock cycles. During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, and the Stack Pointer is incremented by 2. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register - SREG - is not handled by the AVR hardware, neither for interrupts nor for subrou-

20	AT90S8515

AT90S8515

tines. For the interrupt handling routines requiring a storage of the SREG, this must be performed by user software.

For Interrupts triggered by events that can remain static (E.g. the Output Compare Register1 A matching the value

MCU Control Register - MCUCR

of Timer/Counter1) the interrupt flag is set when the event occurs. If the interrupt flag is cleared and the interrupt condition persists, the flag will not be set until the event occurs the next time.

The MCU Control Register contains control bits for general MCU functions.

Bit	7	6	5	4	3	2	1	0
$35 ($55)	SRE	SRW	SE	SM	ISC11	ISC10	ISC01	ISC00	MCUCR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

• Bit 7 - SRE: External SRAM Enable

When the SRE bit is set (one), the external data SRAM is enabled, and the pin functions AD0-7 (Port A), A8-15 (Port C), WR and RD (Port D) are activated as the alternate pin functions. Then the SRE bit overrides any pin direction settings in the respective data direction registers. See “The SRAM Data Memory - Internal and External” for description of the External SRAM pin functions. When the SRE bit is cleared (zero), the external data SRAM is disabled, and the normal pin and data direction settings are used.

• Bit 6 - SRW: External SRAM Wait State

When the SRW bit is set (one), a one cycle wait state is inserted in the external data SRAM access cycle. When the SRW bit is cleared (zero), the external data SRAM access is executed with the normal three-cycle scheme. See Figure 23: External Data SRAM Memory Cycles without Wait State and Figure 24: External Data SRAM Memory Cycles with Wait State.

• Bit 5 - SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.

• Bit 4 - SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph “Sleep Modes” below.

•Bit 3, 2 - ISC11, ISC10: Interrupt Sense Control 1 bit 1 and bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask in the GIMSK is set. The level and edges on the

external INT1 pin that activate the interrupt are defined in the following table:

Table 4. Interrupt 1 Sense Control

ISC11		ISC10	Description
0		0	The low level of INT1 generates an
			interrupt request.
0		1	Reserved
1		0	The falling edge of INT1 generates an
			interrupt request.
1		1	The rising edge of INT1 generates an
			interrupt request.
Note:	When changing the ISC11/ISC10 bits, INT1 must be dis-
	abled by clearing its Interrupt Enable bit in the GIMSK

Register. Otherwise an interrupt can occur when the bits are changed.

•Bit 1, 0 - ISC01, ISC00: Interrupt Sense Control 0 bit 1 and bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set. The level and edges on the external INT0 pin that activate the interrupt are defined in the following table:

Table 5. Interrupt 0 Sense Control

ISC01		ISC00	Description
0		0	The low level of INT0 generates an
			interrupt request.
0		1	Reserved
1		0	The falling edge of INT0 generates an
			interrupt request.
1		1	The rising edge of INT0 generates an
			interrupt request.
Note:	When changing the ISC10/ISC00 bits, INT0 must be dis-
	abled by clearing its Interrupt Enable bit in the GIMSK
	Register. Otherwise an interrupt can occur when the bits
	are changed.

21

Sleep Modes

To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file, SRAM and I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and

The Timer/Counter Prescaler

Figure 31 shows the general Timer/Counter prescaler.

Figure 31. Timer/Counter Prescaler

Status register - ACSR. This will reduce power consumption in Idle Mode.

Power Down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped. The user can select whether the watchdog shall be enabled during power-down mode. If the watchdog is enabled, it will wake up the MCU when the Watchdog Time-out period expires. If the watchdog is disabled, only an external reset or an external level triggered interrupt can wake up the MCU.

Timer / Counters

T h e A T 90 S 8 5 15 pr ov i d e s tw o g e ne r a l pu r p o s e Timer/Counters - one 8-bit T/C and one 16-bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescaling timer. Both Timer/Counters can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.

The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the two Timer/Counters, added selections as CK, external source and stop, can be selected as clock sources.

22	AT90S8515

The 8-Bit Timer/Counter0

Figure 32 shows the block diagram for Timer/Counter0.

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The overflow status flag is found in the Timer/Counter Insterrupt Flag Register - TIFR. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK.

Figure 32. Timer/Counter0 Block Diagram

AT90S8515

When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock.

The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions.

The Timer/Counter0 Control Register - TCCR0

Bit	7	6	5	4	3	2	1	0
$33 ($53)	-	-	-	-	-	CS02	CS01	CS00	TCCR0
Read/Write	R	R	R	R	R	R/W	R/W	R/W
Initial value	0	0	0	0	0	0	0	0

• Bits 7,6 - Res: Reserved bits

These bits are reserved bits in the AT90S8515 and always read zero.

• Bits 2,1,0 - CS02, CS01, CS00: Clock Select0, bit 2,1 and 0

The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.

23