Features
• Compatible with MCS-51™ Products
•8K Bytes of In-System Reprogrammable Downloadable Flash Memory
–SPI Serial Interface for Program Downloading
–Endurance: 1,000 Write/Erase Cycles
•2K Bytes EEPROM
–Endurance: 100,000 Write/Erase Cycles
•4.0V to 6V Operating Range
•Fully Static Operation: 0 Hz to 24 MHz
•Three-Level Program Memory Lock
•256 x 8-bit Internal RAM
•32 Programmable I/O Lines
•Three 16-bit Timer/Counters
•Nine Interrupt Sources
•Programmable UART Serial Channel
•SPI Serial Interface
•Low Power Idle and Power Down Modes
•Interrupt Recovery From Power Down
•Programmable Watchdog Timer
•Dual Data Pointer
•Power Off Flag
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Downloadable Flash programmable and erasable read only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
The AT89S8252 provides the following standard features: 8K bytes of Downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.
The Downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless Lock Bit 2 has been activated.
8-Bit |
Microcontroller |
with 8K Bytes |
Flash |
AT89S8252 |
0401D-A–12/97 |
4-105 |
Pin Configurations
PDIP
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(T2) |
P1.0 |
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1 |
40 |
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VCC |
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(T2 EX) P1.1 |
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2 |
39 |
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P0.0 |
(AD0) |
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P1.2 |
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3 |
38 |
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P0.1 |
(AD1) |
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P1.3 |
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4 |
37 |
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P0.2 |
(AD2) |
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P1.4 |
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5 |
36 |
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P0.3 |
(AD3) |
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(SS) |
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(MOSI) P1.5 |
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6 |
35 |
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P0.4 |
(AD4) |
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(MISO) P1.6 |
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7 |
34 |
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P0.5 |
(AD5) |
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(SCK) P1.7 |
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8 |
33 |
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P0.6 |
(AD6) |
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RST |
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9 |
32 |
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P0.7 |
(AD7) |
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(RXD) P3.0 |
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10 |
31 |
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EA/VPP |
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(TXD) P3.1 |
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30 |
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ALE/PROG |
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P3.2 |
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12 |
29 |
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(INT0) |
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PSEN |
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P3.3 |
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13 |
28 |
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P2.7 |
(A15) |
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(INT1) |
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(T0) P3.4 |
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14 |
27 |
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P2.6 |
(A14) |
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(T1) P3.5 |
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15 |
26 |
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P2.5 |
(A13) |
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P3.6 |
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16 |
25 |
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P2.4 |
(A12) |
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(WR) |
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P3.7 |
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17 |
24 |
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P2.3 |
(A11) |
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(RD) |
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XTAL2 |
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18 |
23 |
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P2.2 |
(A10) |
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XTAL1 |
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19 |
22 |
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P2.1 |
(A9) |
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GND |
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20 |
21 |
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P2.0 |
(A8) |
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PQFP/TQFP
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(SS) |
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(T2 EX) |
(T2) |
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VCC |
(AD0) |
(AD1) |
(AD2) |
(AD3) |
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P1.4 |
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P1.3 |
P1.2 |
P1.1 |
P1.0 |
NC |
P0.0 |
P0.1 |
P0.2 |
P0.3 |
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44 |
43 |
42 |
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40 |
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38 |
37 |
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35 |
34 |
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(MOSI) P1.5 |
1 |
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33 |
P0.4 |
(AD4) |
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(MISO) P1.6 |
2 |
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32 |
P0.5 |
(AD5) |
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(SCK) P1.7 |
3 |
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31 |
P0.6 |
(AD6) |
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RST |
4 |
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30 |
P0.7 |
(AD7) |
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(RXD) P3.0 |
5 |
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29 |
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EA/VPP |
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NC |
6 |
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28 |
NC |
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(TXD) P3.1 |
7 |
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27 |
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ALE/PROG |
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P3.2 |
8 |
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26 |
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(INT0) |
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PSEN |
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P3.3 |
9 |
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25 |
P2.7 |
(A15) |
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(INT1) |
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(T0) P3.4 |
10 |
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24 |
P2.6 |
(A14) |
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(T1) P3.5 |
11 |
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23 |
P2.5 |
(A13) |
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12 |
13 |
14 |
15 |
16 |
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18 |
19 |
20 |
21 |
22 |
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(WR) P3.6 |
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(RD) P3.7 |
XTAL2 |
XTAL1 |
GND |
GND |
(A8) P2.0 |
(A9) P2.1 |
(A10) P2.2 |
(A11) P2.3 |
(A12) P2.4 |
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PLCC
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(SS) |
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(T2 EX) |
(T2) |
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VCC |
(AD0) |
(AD1) |
(AD2) |
(AD3) |
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P1.4 |
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P1.3 |
P1.2 |
P1.1 |
P1.0 |
NC |
P0.0 |
P0.1 |
P0.2 |
P0.3 |
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(MOSI) P1.5 |
6 |
5 |
4 |
3 |
2 |
1 |
44 |
43 |
42 |
41 |
40 |
P0.4 |
(AD4) |
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7 |
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39 |
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(MISO) P1.6 |
8 |
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38 |
P0.5 |
(AD5) |
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(SCK) P1.7 |
9 |
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37 |
P0.6 |
(AD6) |
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RST |
10 |
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36 |
P0.7 |
(AD7) |
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(RXD) P3.0 |
11 |
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35 |
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EA/VPP |
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NC |
12 |
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34 |
NC |
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(TXD) P3.1 |
13 |
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33 |
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ALE/PROG |
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P3.2 |
14 |
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32 |
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(INT0) |
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PSEN |
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P3.3 |
15 |
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31 |
P2.7 |
(A15) |
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(INT1) |
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(T0) P3.4 |
16 |
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30 |
P2.6 |
(A14) |
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(T1) P3.5 |
17 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
29 |
P2.5 |
(A13) |
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18 |
28 |
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(WR) P3.6 |
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(RD) P3.7 |
XTAL2 |
XTAL1 |
GND |
NC |
(A8) P2.0 |
(A9) P2.1 |
(A10) P2.2 |
(A11) P2.3 |
(A12) P2.4 |
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Pin Description
VCC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.
Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.
4-106 AT89S8252
Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.
Port 1
Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively.
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AT89S8252 |
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Block Diagram |
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P0.0 |
- P0.7 |
P2.0 |
- P2.7 |
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VCC |
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PORT 0 DRIVERS |
PORT 2 DRIVERS |
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GND |
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EEPROM |
RAM ADDR. |
RAM |
PORT 0 |
PORT 2 |
FLASH |
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REGISTER |
LATCH |
LATCH |
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B |
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STACK |
PROGRAM |
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ACC |
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ADDRESS |
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REGISTER |
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POINTER |
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REGISTER |
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BUFFER |
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TMP2 |
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TMP1 |
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PC |
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ALU |
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INCREMENTER |
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INTERRUPT, SERIAL PORT, |
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AND TIMER BLOCKS |
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PROGRAM |
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PSW |
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COUNTER |
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PSEN |
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ALE/PROG |
TIMING |
INSTRUCTION |
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DPTR |
AND |
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REGISTER |
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EA / VPP |
CONTROL |
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RST |
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WATCH |
PORT 3 |
PORT 1 |
SPI |
PROGRAM |
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DOG |
LATCH |
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LATCH |
PORT |
LOGIC |
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OSC |
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PORT 3 DRIVERS |
PORT 1 DRIVERS |
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P3.0 - P3.7 |
P1.0 |
- P1.7 |
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4-107 |
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table.
Port Pin |
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Alternate Functions |
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P1.0 |
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T2 (external count input to Timer/Counter 2), |
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clock-out |
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P1.1 |
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T2EX (Timer/Counter 2 capture/reload trigger |
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and direction control) |
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P1.4 |
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(Slave port select input) |
SS |
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P1.5 |
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MOSI (Master data output, slave data input pin |
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for SPI channel) |
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P1.6 |
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MISO (Master data input, slave data output pin |
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for SPI channel) |
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P1.7 |
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SCK (Master clock output, slave clock input pin |
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for SPI channel) |
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Port 1 also receives the low-order address bytes during Flash programming and verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8 bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table.
Port 3 also receives some control signals for Flash programming and verification.
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Port Pin |
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Alternate Functions |
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P3.0 |
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RXD (serial input port) |
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P3.1 |
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TXD (serial output port) |
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P3.2 |
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(external interrupt 0) |
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INT0 |
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P3.3 |
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(external interrupt 1) |
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INT1 |
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P3.4 |
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T0 (timer 0 external input) |
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P3.5 |
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T1 (timer 1 external input) |
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P3.6 |
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(external data memory write strobe) |
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WR |
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P3.7 |
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(external data memory read strobe) |
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RD |
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RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.
ALE/PROG
Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external program memory.
When the AT89S8252 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12volt programming is selected.
4-108 AT89S8252
AT89S8252
XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
XTAL2
Output from the inverting oscillator amplifier.
Table 1. AT89S8252 SFR Map and Reset Values
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
0F8H |
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0FFH |
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0F0H |
B |
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0F7H |
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00000000 |
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0E8H |
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0EFH |
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0E0H |
ACC |
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0E7H |
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00000000 |
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0D8H |
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0DFH |
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0D0H |
PSW |
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SPCR |
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0D7H |
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00000000 |
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000001XX |
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0C8H |
T2CON |
T2MOD |
RCAP2L |
RCAP2H |
TL2 |
TH2 |
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0CFH |
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00000000 |
XXXXXX00 |
00000000 |
00000000 |
00000000 |
00000000 |
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0C0H |
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0C7H |
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0B8H |
IP |
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0BFH |
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XX000000 |
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0B0H |
P3 |
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0B7H |
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11111111 |
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0A8H |
IE |
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SPSR |
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0AFH |
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0X000000 |
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00XXXXXX |
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0A0H |
P2 |
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0A7H |
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11111111 |
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98H |
SCON |
SBUF |
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9FH |
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00000000 |
XXXXXXXX |
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90H |
P1 |
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WMCON |
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97H |
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11111111 |
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00000010 |
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88H |
TCON |
TMOD |
TL0 |
TL1 |
TH0 |
TH1 |
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8FH |
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00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
00000000 |
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80H |
P0 |
SP |
DP0L |
DP0H |
DP1L |
DP1H |
SPDR |
PCON |
87H |
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11111111 |
00000111 |
00000000 |
00000000 |
00000000 |
00000000 |
XXXXXXXX |
0XXX0000 |
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4-109
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16 bit capture mode or 16-bit auto-reload mode.
Watchdog and Memory Control Register The WMCON register contains control bits for the Watchdog Timer (shown in Table 3). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The DPS bit selects one of two DPTR registers available.
SPI Registers Control and status bits for the Serial Peripheral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buffered for writing and the values in SPDR are not changed by Reset.
Interrupt Registers The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In addition, the individual interrupt enable bit for the SPI is in the SPCR register. Two priorities can be set for each of the six interrupt sources in the IP register.
Table 2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H |
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Reset Value = 0000 0000B |
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Bit Addressable |
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TF2 |
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EXF2 |
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RCLK |
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TCLK |
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EXEN2 |
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TR2 |
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C/T2 |
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CP/RL2 |
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7 |
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6 |
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4 |
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2 |
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1 |
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0 |
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TF2 |
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either |
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RCLK = 1 or TCLK = 1. |
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EXF2 |
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. |
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When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be |
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cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). |
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RCLK |
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port |
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Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock. |
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TCLK |
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port |
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Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. |
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EXEN2 |
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if |
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Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. |
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TR2 |
Start/Stop control for Timer 2. TR2 = 1 starts the timer. |
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C/T2 |
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Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered). |
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CP/RL2 |
Capture/Reload select. CP/RL2 |
= 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 |
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causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When |
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either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow. |
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4-110 AT89S8252
AT89S8252
Dual Data Pointer Registers To facilitate accessing both internal EEPROM and external data memory, two banks of 16 bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WMCON selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the
appropriate value before accessing the respective Data Pointer Register.
Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET.
Table 3. WMCON—Watchdog and Memory Control Register
WMCON Address = 96H |
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Reset Value = 0000 0010B |
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PS2 |
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PS1 |
PS0 |
EEMWE |
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EEMEN |
DPS |
WDTRST |
WDTEN |
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7 |
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6 |
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4 |
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0 |
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PS2 |
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Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16 |
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PS1 |
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ms. When all three bits are set to “1”, the nominal period is 2048 ms. |
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PS0 |
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EEMWE |
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EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the |
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MOVX instruction. User software should set this bit to “0” after EEPROM write is completed. |
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EEMEN |
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Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM |
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instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory. |
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DPS |
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Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the |
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second bank, DP1 |
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WDTRST |
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Flag. Each time this bit is set to “1” by user software, a pulse is |
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Watchdog Timer Reset and EEPROM Ready/Busy |
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generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle. |
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RDY/BSY |
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flag in a Read-Only mode during EEPROM write. |
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The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY |
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= 1 means that the EEPROM is ready to be programmed. While programming operations are being executed, |
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RDY/BSY |
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bit equals “0” and is automatically reset to “1” when programming is completed. |
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the RDY/BSY |
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WDTEN |
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Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer. |
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4-111
Table 4. SPCR—SPI Control Register
SPCR Address = D5H |
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Reset Value = 0000 01XXB |
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SPIE |
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SPE |
DORD |
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MSTR |
CPOL |
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CPHA |
SPR1 |
SPR0 |
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7 |
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3 |
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1 |
0 |
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Symbol |
Function |
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SPIE |
SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES |
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= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts. |
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SPE |
SPI Enable. SPI = 1 enables the SPI channel and connects |
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MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and |
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SS, |
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P1.7. SPI = 0 disables the SPI channel. |
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DORD |
Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission. |
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MSTR |
Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode. |
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CPOL |
Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not |
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transmitting. Please refer to figure on SPI Clock Phase and Polarity Control. |
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CPHA |
Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and |
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slave. Please refer to figure on SPI Clock Phase and Polarity Control. |
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SPR0 |
SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have |
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SPR1 |
no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows: |
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SPR1 |
SPR0 |
SCK = FOSC. divided by |
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0 |
0 |
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4 |
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0 |
1 |
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16 |
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1 |
0 |
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64 |
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1 |
1 |
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128 |
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Table 5. SPSR—SPI Status Register
SPSR Address = AAH |
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Reset Value = 00XX XXXXB |
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SPIF |
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WCOL |
— |
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— |
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Bit |
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7 |
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6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Symbol |
Function |
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SPIF |
SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and |
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ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing |
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the SPI data register. |
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WCOL |
Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer, |
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the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF |
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bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register. |
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4-112 AT89S8252
AT89S8252
Table 6. SPDR—SPI Data Register
SPDR Address = 86H |
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Reset Value = unchanged |
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SPD7 |
SPD6 |
SPD5 |
SPD4 |
SPD3 |
SPD2 |
SPD1 |
SPD0 |
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Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
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Data Memory—EEPROM and RAM
The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
The on-chip EEPROM data memory is selected by setting the EEMEN bit in the WMCON register at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. The MOVX instructions are used to access the EEPROM. To access off-chip data memory with the MOVX instructions, the EEMEN bit needs to be set to “0”.
The EEMWE bit in the WMCON register needs to be set to “1” before any byte location in the EEPROM can be written. User software should reset EEMWE bit to “0” if no further EEPROM write is required. EEPROM write cycles in the serial programming mode are self-timed and typically take 2.5 ms. The progress of EEPROM write can be monitored by reading the RDY/BSY bit (read-only) in SFR WMCON. RDY/BSY = 0 means programming is still in progress and RDY/BSY = 1 means EEPROM write cycle is completed and another write cycle can be initiated.
In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the byte being written with the MSB complemented. Once the write cycle is completed, true data are valid at all bit locations.
Programmable Watchdog Timer
The programmable Watchdog Timer (WDT) operates from an independent oscillator. The prescaler bits, PS0, PS1 and PS2 in SFR WMCON are used to set the period of the Watchdog Timer from 16 ms to 2048 ms. The available timer periods are shown in the following table and the actual timer periods (at VCC = 5V) are within ±30% of the nominal.
The WDT is disabled by Power-on Reset and during Power Down. It is enabled by setting the WDTEN bit in SFR WMCON (address = 96H). The WDT is reset by setting the WDTRST bit in WMCON. When the WDT times out without being reset or disabled, an internal RST pulse is generated to reset the CPU.
Table 7. Watchdog Timer Period Selection
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WDT Prescaler Bits |
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Period (nominal) |
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PS2 |
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PS1 |
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PS0 |
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0 |
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0 |
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0 |
16 ms |
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0 |
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0 |
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1 |
32 ms |
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0 |
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1 |
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0 |
64 ms |
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0 |
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1 |
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1 |
128 ms |
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1 |
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0 |
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256 ms |
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1 |
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0 |
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1 |
512 ms |
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1 |
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1 |
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1024 ms |
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1 |
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2048 ms |
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4-113
Timer 0 and 1
Timer 0 and Timer 1 in the AT89S8252 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.”
Timer 2
Timer 2 is a 16 bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 8.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Figure 1. Timer 2 in Capture Mode
Table 8. Timer 2 Operating Modes
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RCLK + TCLK |
CP/RL2 |
TR2 |
MODE |
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0 |
0 |
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1 |
16-bit Auto-Reload |
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0 |
1 |
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1 |
16-bit Capture |
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1 |
X |
1 |
Baud Rate Generator |
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X |
X |
0 |
(Off) |
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Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a l- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when configured in its 16 bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 9). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
OSC ÷12
C/T2 = 0
TH2 |
TL2 |
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TF2 |
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OVERFLOW
CONTROL
TR2
C/T2 = 1
T2 PIN |
CAPTURE |
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RCAP2H RCAP2L
TRANSITION
DETECTOR TIMER 2 INTERRUPT
T2EX PIN |
EXF2 |
CONTROL
EXEN2
4-114 AT89S8252