ATMEL AT89S8252-24JI, AT89S8252-24JC, AT89S8252-24AI, AT89S8252-24AC, AT89S8252-16QA Datasheet

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4 (1)

Features

Compatible with MCS-51™ Products

8K Bytes of In-System Reprogrammable Downloadable Flash Memory

SPI Serial Interface for Program Downloading

Endurance: 1,000 Write/Erase Cycles

2K Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles

4.0V to 6V Operating Range

Fully Static Operation: 0 Hz to 24 MHz

Three-Level Program Memory Lock

256 x 8-bit Internal RAM

32 Programmable I/O Lines

Three 16-bit Timer/Counters

Nine Interrupt Sources

Programmable UART Serial Channel

SPI Serial Interface

Low Power Idle and Power Down Modes

Interrupt Recovery From Power Down

Programmable Watchdog Timer

Dual Data Pointer

Power Off Flag

Description

The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Downloadable Flash programmable and erasable read only memory and 2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

The AT89S8252 provides the following standard features: 8K bytes of Downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset.

The Downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless Lock Bit 2 has been activated.

8-Bit

Microcontroller

with 8K Bytes

Flash

AT89S8252

0401D-A–12/97

4-105

Pin Configurations

PDIP

 

 

(T2)

P1.0

 

1

40

 

VCC

 

 

(T2 EX) P1.1

 

2

39

 

P0.0

(AD0)

 

 

 

 

 

 

 

P1.2

 

3

38

 

P0.1

(AD1)

 

 

 

 

 

 

 

P1.3

 

4

37

 

P0.2

(AD2)

 

 

 

 

 

 

P1.4

 

5

36

 

P0.3

(AD3)

(SS)

 

 

(MOSI) P1.5

 

6

35

 

P0.4

(AD4)

(MISO) P1.6

 

7

34

 

P0.5

(AD5)

(SCK) P1.7

 

8

33

 

P0.6

(AD6)

 

 

 

 

 

 

 

RST

 

9

32

 

P0.7

(AD7)

(RXD) P3.0

 

10

31

 

 

 

 

 

 

 

EA/VPP

(TXD) P3.1

 

11

30

 

 

 

 

 

 

ALE/PROG

 

 

 

 

P3.2

 

12

29

 

 

 

 

(INT0)

 

 

PSEN

 

 

 

 

P3.3

 

13

28

 

P2.7

(A15)

(INT1)

 

 

 

 

(T0) P3.4

 

14

27

 

P2.6

(A14)

 

 

(T1) P3.5

 

15

26

 

P2.5

(A13)

 

 

 

 

P3.6

 

16

25

 

P2.4

(A12)

 

(WR)

 

 

 

 

 

P3.7

 

17

24

 

P2.3

(A11)

 

(RD)

 

 

 

 

 

 

XTAL2

 

18

23

 

P2.2

(A10)

 

 

 

 

XTAL1

 

19

22

 

P2.1

(A9)

 

 

 

 

 

 

 

GND

 

20

21

 

P2.0

(A8)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PQFP/TQFP

 

 

 

 

(SS)

 

 

 

(T2 EX)

(T2)

 

VCC

(AD0)

(AD1)

(AD2)

(AD3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4

 

P1.3

P1.2

P1.1

P1.0

NC

P0.0

P0.1

P0.2

P0.3

 

 

 

 

 

 

 

 

44

43

42

41

40

39

38

37

36

35

34

 

 

 

 

 

(MOSI) P1.5

1

 

 

 

 

 

 

 

 

 

 

 

33

P0.4

(AD4)

(MISO) P1.6

2

 

 

 

 

 

 

 

 

 

 

 

32

P0.5

(AD5)

(SCK) P1.7

3

 

 

 

 

 

 

 

 

 

 

 

31

P0.6

(AD6)

 

 

RST

4

 

 

 

 

 

 

 

 

 

 

 

30

P0.7

(AD7)

(RXD) P3.0

5

 

 

 

 

 

 

 

 

 

 

 

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA/VPP

 

 

NC

6

 

 

 

 

 

 

 

 

 

 

 

28

NC

 

 

 

(TXD) P3.1

7

 

 

 

 

 

 

 

 

 

 

 

27

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/PROG

 

 

P3.2

8

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

(INT0)

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

P3.3

9

 

 

 

 

 

 

 

 

 

 

 

25

P2.7

(A15)

(INT1)

 

 

 

 

 

 

 

 

 

 

 

(T0) P3.4

10

 

 

 

 

 

 

 

 

 

 

 

24

P2.6

(A14)

 

(T1) P3.5

11

 

 

 

 

 

 

 

 

 

 

 

23

P2.5

(A13)

 

 

 

12

13

14

15

16

17

18

19

20

21

22

 

 

 

 

 

 

 

 

 

(WR) P3.6

 

(RD) P3.7

XTAL2

XTAL1

GND

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC

 

 

 

 

(SS)

 

 

 

(T2 EX)

(T2)

 

VCC

(AD0)

(AD1)

(AD2)

(AD3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P1.4

 

P1.3

P1.2

P1.1

P1.0

NC

P0.0

P0.1

P0.2

P0.3

 

 

 

 

 

(MOSI) P1.5

6

5

4

3

2

1

44

43

42

41

40

P0.4

(AD4)

7

 

 

 

 

 

 

 

 

 

 

 

39

(MISO) P1.6

8

 

 

 

 

 

 

 

 

 

 

 

38

P0.5

(AD5)

(SCK) P1.7

9

 

 

 

 

 

 

 

 

 

 

 

37

P0.6

(AD6)

 

 

RST

10

 

 

 

 

 

 

 

 

 

 

36

P0.7

(AD7)

(RXD) P3.0

11

 

 

 

 

 

 

 

 

 

 

35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EA/VPP

 

 

NC

12

 

 

 

 

 

 

 

 

 

 

34

NC

 

 

 

(TXD) P3.1

13

 

 

 

 

 

 

 

 

 

 

33

 

 

 

 

 

 

 

 

 

 

 

 

 

ALE/PROG

 

 

P3.2

14

 

 

 

 

 

 

 

 

 

 

32

 

 

 

 

(INT0)

 

 

 

 

 

 

 

 

 

 

PSEN

 

 

P3.3

15

 

 

 

 

 

 

 

 

 

 

31

P2.7

(A15)

(INT1)

 

 

 

 

 

 

 

 

 

 

 

(T0) P3.4

16

 

 

 

 

 

 

 

 

 

 

30

P2.6

(A14)

 

(T1) P3.5

17

19

20

21

22

23

24

25

26

27

29

P2.5

(A13)

 

 

 

18

28

 

 

 

 

 

 

 

 

 

(WR) P3.6

 

(RD) P3.7

XTAL2

XTAL1

GND

NC

(A8) P2.0

(A9) P2.1

(A10) P2.2

(A11) P2.3

(A12) P2.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.

4-106 AT89S8252

Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Some Port 1 pins provide additional functions. P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively.

ATMEL AT89S8252-24JI, AT89S8252-24JC, AT89S8252-24AI, AT89S8252-24AC, AT89S8252-16QA Datasheet

 

 

 

 

 

 

AT89S8252

Block Diagram

 

 

 

 

 

 

 

 

 

P0.0

- P0.7

P2.0

- P2.7

 

VCC

 

 

 

 

 

 

 

 

 

 

PORT 0 DRIVERS

PORT 2 DRIVERS

 

GND

 

 

 

 

 

 

 

 

EEPROM

RAM ADDR.

RAM

PORT 0

PORT 2

FLASH

 

 

 

 

 

REGISTER

LATCH

LATCH

 

 

B

 

 

 

STACK

PROGRAM

 

ACC

 

 

ADDRESS

 

REGISTER

 

 

POINTER

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUFFER

 

 

TMP2

 

TMP1

 

 

 

 

 

 

 

 

 

 

PC

 

 

 

ALU

 

 

 

INCREMENTER

 

 

 

 

INTERRUPT, SERIAL PORT,

 

 

 

 

 

 

AND TIMER BLOCKS

 

 

 

 

 

 

 

 

PROGRAM

 

 

 

PSW

 

 

 

COUNTER

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

ALE/PROG

TIMING

INSTRUCTION

 

 

 

 

DPTR

AND

 

 

 

 

 

REGISTER

 

 

 

 

EA / VPP

CONTROL

 

 

 

 

 

 

 

 

 

 

 

RST

 

 

 

 

 

 

 

 

 

WATCH

PORT 3

PORT 1

SPI

PROGRAM

 

 

DOG

LATCH

 

LATCH

PORT

LOGIC

 

OSC

 

 

 

 

 

 

 

 

 

PORT 3 DRIVERS

PORT 1 DRIVERS

 

 

 

 

P3.0 - P3.7

P1.0

- P1.7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4-107

Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table.

Port Pin

 

Alternate Functions

 

 

 

P1.0

 

T2 (external count input to Timer/Counter 2),

 

 

clock-out

 

 

 

P1.1

 

T2EX (Timer/Counter 2 capture/reload trigger

 

 

and direction control)

 

 

 

 

P1.4

 

 

(Slave port select input)

SS

 

 

 

P1.5

 

MOSI (Master data output, slave data input pin

 

 

for SPI channel)

 

 

 

P1.6

 

MISO (Master data input, slave data output pin

 

 

for SPI channel)

 

 

 

P1.7

 

SCK (Master clock output, slave clock input pin

 

 

for SPI channel)

 

 

 

 

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8 bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table.

Port 3 also receives some control signals for Flash programming and verification.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port Pin

 

Alternate Functions

 

 

 

P3.0

 

RXD (serial input port)

 

 

 

P3.1

 

TXD (serial output port)

 

 

 

 

 

 

P3.2

 

 

 

 

(external interrupt 0)

 

INT0

 

 

 

 

 

 

P3.3

 

 

 

 

(external interrupt 1)

 

INT1

 

 

 

P3.4

 

T0 (timer 0 external input)

 

 

 

P3.5

 

T1 (timer 1 external input)

 

 

 

 

 

P3.6

 

 

 

(external data memory write strobe)

 

WR

 

 

 

 

P3.7

 

 

(external data memory read strobe)

RD

 

 

 

 

 

 

 

 

 

 

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT89S8252 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12volt programming is selected.

4-108 AT89S8252

AT89S8252

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT89S8252 SFR Map and Reset Values

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

0F8H

 

 

 

 

 

 

 

 

0FFH

 

 

 

 

 

 

 

 

 

 

0F0H

B

 

 

 

 

 

 

 

0F7H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E8H

 

 

 

 

 

 

 

 

0EFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E0H

ACC

 

 

 

 

 

 

 

0E7H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D8H

 

 

 

 

 

 

 

 

0DFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D0H

PSW

 

 

 

 

SPCR

 

 

0D7H

00000000

 

 

 

 

000001XX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C8H

T2CON

T2MOD

RCAP2L

RCAP2H

TL2

TH2

 

 

0CFH

00000000

XXXXXX00

00000000

00000000

00000000

00000000

 

 

 

 

 

 

0C0H

 

 

 

 

 

 

 

 

0C7H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B8H

IP

 

 

 

 

 

 

 

0BFH

XX000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B0H

P3

 

 

 

 

 

 

 

0B7H

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0A8H

IE

 

SPSR

 

 

 

 

 

0AFH

0X000000

 

00XXXXXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0A0H

P2

 

 

 

 

 

 

 

0A7H

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

98H

SCON

SBUF

 

 

 

 

 

 

9FH

00000000

XXXXXXXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

90H

P1

 

 

 

 

 

WMCON

 

97H

11111111

 

 

 

 

 

00000010

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

88H

TCON

TMOD

TL0

TL1

TH0

TH1

 

 

8FH

00000000

00000000

00000000

00000000

00000000

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80H

P0

SP

DP0L

DP0H

DP1L

DP1H

SPDR

PCON

87H

11111111

00000111

00000000

00000000

00000000

00000000

XXXXXXXX

0XXX0000

 

 

 

 

 

 

 

 

 

 

 

 

4-109

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16 bit capture mode or 16-bit auto-reload mode.

Watchdog and Memory Control Register The WMCON register contains control bits for the Watchdog Timer (shown in Table 3). The EEMEN and EEMWE bits are used to select the 2K bytes on-chip EEPROM, and to enable byte-write. The DPS bit selects one of two DPTR registers available.

SPI Registers Control and status bits for the Serial Peripheral Interface are contained in registers SPCR (shown in Table 4) and SPSR (shown in Table 5). The SPI data bits are contained in the SPDR register. Writing the SPI data register during serial data transfer sets the Write Collision bit, WCOL, in the SPSR register. The SPDR is double buffered for writing and the values in SPDR are not changed by Reset.

Interrupt Registers The global interrupt enable bit and the individual interrupt enable bits are in the IE register. In addition, the individual interrupt enable bit for the SPI is in the SPCR register. Two priorities can be set for each of the six interrupt sources in the IP register.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value = 0000 0000B

Bit Addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF2

 

EXF2

 

RCLK

 

 

TCLK

 

EXEN2

 

TR2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T2

 

 

CP/RL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

7

 

6

 

5

 

4

 

3

 

 

2

 

1

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF2

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either

 

 

 

 

 

 

RCLK = 1 or TCLK = 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXF2

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

 

 

 

 

 

 

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be

 

 

 

 

 

 

cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

 

 

 

 

 

 

 

 

RCLK

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

 

 

 

 

 

 

Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.

 

 

 

 

 

 

 

 

 

 

 

 

TCLK

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port

 

 

 

 

 

 

Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

 

 

 

 

 

 

 

 

 

 

 

 

EXEN2

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

 

 

 

 

 

 

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TR2

Start/Stop control for Timer 2. TR2 = 1 starts the timer.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T2

 

 

 

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP/RL2

Capture/Reload select. CP/RL2

= 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0

 

 

 

 

 

 

causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When

 

 

 

 

 

 

either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4-110 AT89S8252

AT89S8252

Dual Data Pointer Registers To facilitate accessing both internal EEPROM and external data memory, two banks of 16 bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR WMCON selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the

appropriate value before accessing the respective Data Pointer Register.

Power Off Flag The Power Off Flag (POF) is located at bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by RESET.

Table 3. WMCON—Watchdog and Memory Control Register

WMCON Address = 96H

 

 

 

 

 

 

 

 

 

Reset Value = 0000 0010B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PS2

 

 

 

PS1

PS0

EEMWE

 

EEMEN

DPS

WDTRST

WDTEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

7

 

 

 

 

6

5

4

 

 

3

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PS2

 

Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16

PS1

 

ms. When all three bits are set to “1”, the nominal period is 2048 ms.

 

 

 

 

PS0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EEMWE

 

EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the

 

 

 

 

MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.

 

 

 

 

 

EEMEN

 

Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM

 

 

 

 

instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory.

 

 

 

DPS

 

Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the

 

 

 

 

second bank, DP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDTRST

 

 

 

 

 

 

 

 

 

 

 

Flag. Each time this bit is set to “1” by user software, a pulse is

 

Watchdog Timer Reset and EEPROM Ready/Busy

 

 

 

 

generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle.

RDY/BSY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

flag in a Read-Only mode during EEPROM write.

 

 

 

 

The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY

 

 

 

 

 

 

 

 

= 1 means that the EEPROM is ready to be programmed. While programming operations are being executed,

 

 

 

 

RDY/BSY

 

 

 

 

 

 

 

bit equals “0” and is automatically reset to “1” when programming is completed.

 

 

 

 

 

 

the RDY/BSY

 

 

 

 

 

WDTEN

 

Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4-111

Table 4. SPCR—SPI Control Register

SPCR Address = D5H

 

 

 

 

 

 

 

 

 

Reset Value = 0000 01XXB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPIE

 

SPE

DORD

 

MSTR

CPOL

 

CPHA

SPR1

SPR0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

7

 

6

5

 

4

3

 

 

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPIE

SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES

 

 

= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.

 

 

 

 

 

 

 

 

SPE

SPI Enable. SPI = 1 enables the SPI channel and connects

 

MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and

SS,

 

 

P1.7. SPI = 0 disables the SPI channel.

 

 

 

 

 

 

 

 

 

 

 

DORD

Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.

 

 

 

 

MSTR

Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.

 

 

 

 

CPOL

Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not

 

 

transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.

 

 

 

 

 

CPHA

Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and

 

 

slave. Please refer to figure on SPI Clock Phase and Polarity Control.

 

 

 

 

 

 

SPR0

SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have

SPR1

no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows:

 

 

 

 

SPR1

SPR0

SCK = FOSC. divided by

 

 

 

 

 

 

 

 

0

0

 

4

 

 

 

 

 

 

 

 

 

 

 

 

0

1

 

16

 

 

 

 

 

 

 

 

 

 

 

 

1

0

 

64

 

 

 

 

 

 

 

 

 

 

 

 

1

1

 

128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 5. SPSR—SPI Status Register

SPSR Address = AAH

 

 

 

 

 

Reset Value = 00XX XXXXB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPIF

 

WCOL

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

7

 

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

Function

 

 

 

 

 

 

 

 

 

 

SPIF

SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and

 

 

ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing

 

 

the SPI data register.

 

 

 

 

 

 

 

 

 

WCOL

Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer,

 

 

the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF

 

 

bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.

 

 

 

 

 

 

 

 

 

 

 

 

4-112 AT89S8252

AT89S8252

Table 6. SPDR—SPI Data Register

SPDR Address = 86H

 

 

 

 

 

Reset Value = unchanged

 

 

 

 

 

 

 

 

 

 

SPD7

SPD6

SPD5

SPD4

SPD3

SPD2

SPD1

SPD0

 

 

 

 

 

 

 

 

 

Bit

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

Data Memory—EEPROM and RAM

The AT89S8252 implements 2K bytes of on-chip EEPROM for data storage and 256 bytes of RAM. The upper 128 bytes of RAM occupy a parallel space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

The on-chip EEPROM data memory is selected by setting the EEMEN bit in the WMCON register at SFR address location 96H. The EEPROM address range is from 000H to 7FFH. The MOVX instructions are used to access the EEPROM. To access off-chip data memory with the MOVX instructions, the EEMEN bit needs to be set to “0”.

The EEMWE bit in the WMCON register needs to be set to “1” before any byte location in the EEPROM can be written. User software should reset EEMWE bit to “0” if no further EEPROM write is required. EEPROM write cycles in the serial programming mode are self-timed and typically take 2.5 ms. The progress of EEPROM write can be monitored by reading the RDY/BSY bit (read-only) in SFR WMCON. RDY/BSY = 0 means programming is still in progress and RDY/BSY = 1 means EEPROM write cycle is completed and another write cycle can be initiated.

In addition, during EEPROM programming, an attempted read from the EEPROM will fetch the byte being written with the MSB complemented. Once the write cycle is completed, true data are valid at all bit locations.

Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) operates from an independent oscillator. The prescaler bits, PS0, PS1 and PS2 in SFR WMCON are used to set the period of the Watchdog Timer from 16 ms to 2048 ms. The available timer periods are shown in the following table and the actual timer periods (at VCC = 5V) are within ±30% of the nominal.

The WDT is disabled by Power-on Reset and during Power Down. It is enabled by setting the WDTEN bit in SFR WMCON (address = 96H). The WDT is reset by setting the WDTRST bit in WMCON. When the WDT times out without being reset or disabled, an internal RST pulse is generated to reset the CPU.

Table 7. Watchdog Timer Period Selection

 

WDT Prescaler Bits

 

Period (nominal)

 

 

 

 

 

 

PS2

 

PS1

 

PS0

 

 

 

 

 

 

 

0

 

0

 

0

16 ms

 

 

 

 

 

 

0

 

0

 

1

32 ms

 

 

 

 

 

 

0

 

1

 

0

64 ms

 

 

 

 

 

 

0

 

1

 

1

128 ms

 

 

 

 

 

 

1

 

0

 

0

256 ms

 

 

 

 

 

 

1

 

0

 

1

512 ms

 

 

 

 

 

 

1

 

1

 

0

1024 ms

 

 

 

 

 

 

1

 

1

 

1

2048 ms

 

 

 

 

 

 

4-113

Timer 0 and 1

Timer 0 and Timer 1 in the AT89S8252 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, “Timer/Counters.”

Timer 2

Timer 2 is a 16 bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 8.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Figure 1. Timer 2 in Capture Mode

Table 8. Timer 2 Operating Modes

 

 

 

 

 

 

RCLK + TCLK

CP/RL2

TR2

MODE

 

 

 

 

 

 

0

0

 

1

16-bit Auto-Reload

 

 

 

 

 

 

0

1

 

1

16-bit Capture

 

 

 

 

 

 

1

X

1

Baud Rate Generator

 

 

 

 

 

 

X

X

0

(Off)

 

 

 

 

 

 

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a l- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16 bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 9). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

OSC ÷12

C/T2 = 0

TH2

TL2

 

 

TF2

 

 

 

 

 

 

 

 

 

 

OVERFLOW

CONTROL

TR2

C/T2 = 1

T2 PIN

CAPTURE

 

RCAP2H RCAP2L

TRANSITION

DETECTOR TIMER 2 INTERRUPT

T2EX PIN

EXF2

CONTROL

EXEN2

4-114 AT89S8252

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