ATMEL AT89C51-20JC, AT89C51-20AI, AT89C51-20AC, AT89C51-16QI, AT89C51-16QC Datasheet

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Features

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compatible with MCS-51™ Products

 

 

 

 

 

 

 

 

 

 

 

 

4K Bytes of In-System Reprogrammable Flash Memory

 

 

 

 

 

 

 

 

 

 

 

– Endurance: 1,000 Write/Erase Cycles

 

 

 

 

 

 

 

 

 

 

 

Fully Static Operation: 0 Hz to 24 MHz

 

 

 

 

 

 

 

 

 

 

 

Three-Level Program Memory Lock

 

 

 

 

 

 

 

 

 

 

 

 

128 x 8-Bit Internal RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

32 Programmable I/O Lines

 

 

 

 

 

 

 

 

 

 

 

 

 

Two 16-Bit Timer/Counters

 

 

 

 

 

 

 

 

 

 

 

 

 

Six Interrupt Sources

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8-Bit

Programmable Serial Channel

 

 

 

 

 

 

 

 

 

 

 

Low Power Idle and Power Down Modes

 

 

 

 

 

 

 

 

 

 

Microcontroller

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

with 4K Bytes

The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K

bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The

Flash

device is manufactured using Atmel’s high density nonvolatile memory technology

and is compatible with the industry standard MCS-51™ instruction set and pinout. The

 

on-chip Flash allows the program memory to be reprogrammed in-system or by a con-

AT89C51

ventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with

Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer which

 

provides a highly flexible and cost effective solution to many embedded control appli-

 

cations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(continued)

 

Pin Configurations

 

 

 

 

 

PDIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 0

 

1

 

4 0

 

V C C

 

 

 

 

 

 

 

 

 

 

 

P 1 . 1

 

2

 

3 9

 

P 0 . 0 ( A D 0 )

 

 

 

 

 

 

 

 

 

 

P 1 . 2

 

3

 

3 8

 

P 0 . 1 ( A D 1 )

 

 

 

 

 

 

 

 

 

 

P 1 . 3

 

4

 

3 7

 

P 0 . 2 ( A D 2 )

 

 

 

 

 

 

 

 

 

 

P 1 . 4

 

5

 

3 6

 

P 0 . 3 ( A D 3 )

 

 

 

 

 

 

 

 

 

 

P 1 . 5

 

6

 

3 5

 

P 0 . 4 ( A D 4 )

 

 

 

 

 

 

 

 

 

 

P 1 . 6

 

7

 

3 4

 

P 0 . 5 ( A D 5 )

 

 

 

 

 

 

 

 

 

 

P 1 . 7

 

8

 

3 3

 

P 0 . 6 ( A D 6 )

 

 

 

 

 

 

 

 

 

 

R S T

 

9

 

3 2

 

P 0 . 7 ( A D 7 )

 

 

 

PQFP/TQFP

 

 

( R X D ) P 3 . 0

 

1 0

 

3 1 E A / V P P

 

 

 

 

 

( T X D ) P 3 . 1

 

1 1

 

3 0 A L E / P R O G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

) ) ) )

 

( I N T 0 ) P 3 . 2

 

1 2

 

2 9

 

P S E N

 

 

 

 

 

 

 

 

D0 D1 D2 D3

 

( I N T 1 ) P 3 . 3

 

1 3

 

2 8

 

P 2 . 7 ( A 1 5 )

 

 

I N D E X

 

 

 

 

(A (A (A (A

 

( T 0 ) P 3 . 4

 

1 4

 

2 7

 

P 2 . 6 ( A 1 4 )

 

 

1.4 1.3 1.2 1.1 1.0 C

CC

0.0 0.1 0.2 0.3

 

( T 1 ) P 3 . 5

 

1 5

 

2 6

 

P 2 . 5 ( A 1 3 )

 

 

C O R N E R

 

( W R ) P 3 . 6

 

1 6

 

2 5

 

P 2 . 4 ( A 1 2 )

 

 

 

P P P P P N

V

P P P P

 

( R D ) P 3 . 7

 

1 7

 

2 4

 

P 2 . 3 ( A 1 1 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 4

4 2

4 0

3 8

3 6

3 4

 

X TA L 2

 

1 8

 

2 3

 

P 2 . 2 ( A 1 0 )

 

 

 

 

X TA L 1

 

1 9

 

2 2

 

P 2 . 1 ( A 9 )

 

 

 

4 3

 

4 1 3 9

3 7 3 5

 

 

 

 

 

 

P 1 . 5

1

 

 

 

 

3 3

P 0 . 4 ( A D 4 )

G N D

 

2 0

 

2 1

 

P 2 . 0 ( A 8 )

 

 

P 1 . 6

2

 

 

 

 

3 2

P 0 . 5 ( A D 5 )

 

 

 

PLCC

 

 

 

 

 

 

P 1 . 7

3

 

 

 

 

3 1

P 0 . 6 ( A D 6 )

 

 

 

 

 

 

 

 

 

R S T

4

 

 

 

 

3 0

P 0 . 7 ( A D 7 )

 

 

 

 

 

 

0) 1) 2) 3)

 

 

 

( R X D ) P 3 . 0

5

 

 

 

 

2 9

E A / V P P

 

 

 

 

 

 

 

 

 

N C

6

 

 

 

 

2 8

N C

 

 

 

 

 

 

D D D D

 

 

 

 

 

 

 

 

 

 

 

 

 

(A (A (A (A

 

 

 

( T X D ) P 3 . 1

7

 

 

 

 

2 7

A L E / P R O G

 

 

 

 

 

 

 

 

( I N T 0 ) P 3 . 2

8

 

 

 

 

2 6

P S E N

I N D E X

1P.4 1P.3

1P.2 1P.1 1P.0 CN

CVC

0P.0 0P.1 0P.2 0P.3

 

 

 

( T 0 ) P 3 . 4

1 0

 

 

 

 

2 4

P 2 . 6 ( A 1 4 )

C O R N E R

 

 

( I N T 1 ) P 3 . 3

9

 

 

 

 

2 5

P 2 . 7 ( A 1 5 )

 

 

 

 

 

 

 

 

 

 

 

( T 1 ) P 3 . 5

1 1

 

 

 

 

2 3

P 2 . 5 ( A 1 3 )

 

6

 

4

2

4 4

 

4 2

4 0

 

 

 

 

 

 

 

 

1 9

2 12 2

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 5

7

5

3

1

4 3 4 13 9

P 0 . 4 ( A D 4 )

 

 

 

1 21 31 41 51 61 71 8 2 0

 

 

 

 

.3P6 .3P7 LTA2 LTA1 DNG DNG .2P0 .2P1 .2P2 .2P3 .2P4

 

P 1 . 6

8

 

 

 

 

 

 

3 8

P 0 . 5 ( A D 5 )

 

 

 

 

P 1 . 7

9

 

 

 

 

 

 

3 7

P 0 . 6 ( A D 6 )

 

 

 

 

 

 

 

 

 

 

R S T 1 0

 

 

 

 

 

 

3 6

P 0 . 7 ( A D 7 )

 

 

 

) ) X X

) ) ) ) )

 

( R X D ) P 3 . 0

1 1

 

 

 

 

 

 

3 5 E A / V P P

 

 

 

RW( DR(

 

 

8A( 9A( 01A( 11A( 21A(

 

N C

1 2

 

 

 

 

 

 

3 4

N C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T X D ) P 3 . 1

1 3

 

 

 

 

 

 

3 3 A L E / P R O G

 

 

 

 

 

 

 

 

 

 

( I N T 0 ) P 3 . 2

1 4

 

 

 

 

 

 

3 2 P S E N

 

 

 

 

 

 

 

 

 

 

( I N T 1 ) P 3 . 3

1 5

 

 

 

 

 

 

3 1

P 2 . 7 ( A 1 5 )

 

 

 

 

 

 

 

 

 

 

( T 0 ) P 3 . 4

1 6

 

 

 

 

 

 

3 0

P 2 . 6 ( A 1 4 )

 

 

 

 

 

 

 

 

 

 

( T 1 ) P 3 . 5

1 7

1 9 2 1

2 3

2 5 2 72 9

P 2 . 5 ( A 1 3 )

 

 

 

 

 

 

 

 

 

 

 

1 8

 

2 0

2 2

2 4

2 6

2 8

 

 

 

 

 

 

 

 

 

 

 

 

P3.6 P3.7 TAL2 TAL1 GND NC P2.0 P2.1 P2.2 P2.3 P2.4

 

 

 

 

 

 

 

 

 

 

 

 

RW() DR()

X X

 

8A() 9A() 01A() 11A() 21A()

 

0265F-A–12/97

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4-29

ATMEL AT89C51-20JC, AT89C51-20AI, AT89C51-20AC, AT89C51-16QI, AT89C51-16QC Datasheet

Block Diagram

 

 

 

 

 

 

 

 

 

P0.0

- P0.7

P2.0

- P2.7

 

VCC

 

 

 

 

 

 

 

 

 

 

PORT 0 DRIVERS

PORT 2 DRIVERS

 

GND

 

 

 

 

 

 

 

 

RAM ADDR.

RAM

PORT 0

PORT 2

FLASH

 

 

REGISTER

LATCH

LATCH

 

 

 

 

 

 

B

 

 

 

STACK

PROGRAM

 

ACC

 

 

ADDRESS

 

REGISTER

 

 

POINTER

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

TMP2

TMP1

 

 

BUFFER

 

 

 

 

 

 

 

 

 

 

 

 

 

PC

 

 

 

ALU

 

 

 

INCREMENTER

 

 

 

 

INTERRUPT, SERIAL PORT,

 

 

 

 

 

 

AND TIMER BLOCKS

 

 

 

 

 

 

 

 

PROGRAM

 

 

 

PSW

 

 

 

COUNTER

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

ALE/PROG

TIMING

INSTRUCTION

 

 

 

 

DPTR

AND

 

 

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

EA / VPP

CONTROL

 

 

 

 

 

 

 

 

 

 

 

RST

 

 

 

 

 

 

 

 

 

 

PORT 1

PORT 3

 

 

 

 

LATCH

 

LATCH

 

 

OSC

 

 

 

 

 

 

 

 

 

PORT 1 DRIVERS

PORT 3 DRIVERS

 

 

 

 

P1.0 - P1.7

P3.0

- P3.7

 

 

 

 

 

 

 

4-30

 

AT89C51

 

 

 

 

The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.

Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups

AT89C51

when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT89C51 as listed below:

Port Pin

Alternate Functions

 

 

 

P3.0

 

RXD (serial input port)

 

 

 

P3.1

 

TXD (serial output port)

 

 

 

 

 

 

 

P3.2

 

 

 

 

 

(external interrupt 0)

 

INT0

 

 

 

 

 

 

P3.3

 

 

 

 

 

(external interrupt 1)

 

INT1

 

 

 

P3.4

 

T0 (timer 0 external input)

 

 

 

P3.5

 

T1 (timer 1 external input)

 

 

 

 

 

P3.6

 

 

 

(external data memory write strobe)

 

WR

 

 

 

 

P3.7

 

 

(external data memory read strobe)

RD

 

 

 

 

 

 

 

Port 3 also receives some control signals for Flash programming and verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

4-31

When the AT89C51 is executing code from external program memory, PSEN is activated twice each machine

cycle, except that two PSEN activations are skipped during each access to external data memory.

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Figure 1. Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 2. External Clock Drive Configuration

Idle Mode

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

Status of External Pins During Idle and Power Down Modes

 

 

 

 

 

 

 

 

 

 

Mode

Program Memory

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

 

 

 

 

 

 

 

 

 

 

Idle

Internal

1

1

 

Data

Data

Data

Data

 

 

 

 

 

 

 

 

 

 

Idle

External

1

1

 

Float

Data

Address

Data

 

 

 

 

 

 

 

 

 

 

Power Down

Internal

0

0

 

Data

Data

Data

Data

 

 

 

 

 

 

 

 

 

 

Power Down

External

0

0

 

Float

Data

Data

Data

 

 

 

 

 

 

 

 

 

 

4-32

AT89C51

 

 

 

Power Down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

AT89C51

Program Memory Lock Bits

On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

Lock Bit Protection Modes

 

Program Lock Bits

 

Protection Type

 

 

 

 

 

 

 

 

 

 

 

LB1

LB2

 

LB3

 

 

 

 

 

 

 

 

 

 

1

 

U

U

 

U

No program lock features.

 

 

 

 

 

 

 

2

 

P

U

 

U

MOVC instructions executed from external program memory are disabled from fetching code

 

 

 

 

 

 

bytes from internal memory,

EA

is sampled and latched on reset, and further programming of the

 

 

 

 

 

 

Flash is disabled.

 

 

 

 

 

 

 

3

 

P

P

 

U

Same as mode 2, also verify is disabled.

 

 

 

 

 

 

 

4

 

P

P

 

P

Same as mode 3, also external execution is disabled.

 

 

 

 

 

 

 

 

 

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers.

The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table.

 

VPP = 12V

VPP = 5V

Top-Side Mark

AT89C51

AT89C51

 

xxxx

xxxx-5

 

yyww

yyww

 

 

 

Signature

(030H)=1EH

(030H)=1EH

 

(031H)=51H

(031H)=51H

 

(032H)=FFH

(032H)=05H

 

 

 

The AT89C51 code memory array is programmed byte-by- byte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.

Programming Algorithm: Before programming the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps.

1.Input the desired memory location on the address lines.

2.Input the appropriate data byte on the data lines.

3.Activate the correct combination of control signals.

4.Raise EA/VPP to 12V for the high-voltage programming mode.

5.Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.

Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle

has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.

4-33

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