ATMEL AT87F52-24PI, AT87F52-24PC, AT87F52-24JI, AT87F52-24JC, AT87F52-24AI Datasheet

...
0 (0)

Features

Compatible with MCS-51™ Products

8K Bytes of User Programmable QuickFlash™ Memory

Fully Static Operation: 0 Hz to 24 MHz

Three-Level Program Memory Lock

256 x 8-Bit Internal RAM

32 Programmable I/O Lines

Three 16-Bit Timer/Counters

Eight Interrupt Sources

Programmable Serial Channel

Low Power Idle and Power Down Modes

Description

The AT87F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of QuickFlash programmable read only memory. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip QuickFlash allows the program memory to be user programmed by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT87F52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.

Pin Configurations

TQFP

I N D E X

C O R N E R

 

 

 

 

 

P 1 . 5

 

 

 

 

 

P 1 . 6

 

 

 

 

 

P 1 . 7

 

 

 

 

 

R S T

( R X D )

P 3 . 0

 

 

 

 

 

N C

 

( T X D )

P 3 . 1

( I

N T 0

)

P 3 . 2

(

I N T 1

)

P 3 . 3

 

 

( T 0 )

P 3 . 4

 

 

( T 1 )

P 3 . 5

 

 

 

 

 

 

2 EX) 2)

 

 

 

 

D0) D1) D2) D3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(T (T

 

 

 

 

(A (A (A (A

 

 

 

 

 

 

 

 

 

P1.4 P1.3 P1.2 P1.1 P1.0 NC

VCC

P0.0 P0.1 P0.2 P0.3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4 4

 

4 2

4 0

 

 

3 8

3 6

3 4

 

 

 

 

 

 

 

 

4 3

 

 

4 1

 

3 9

 

3 7

 

3 5

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 3

 

 

P 0 . 4 ( A D 4 )

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

 

P 0 . 5 ( A D 5 )

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 1

 

 

P 0 . 6 ( A D 6 )

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 0

 

 

P 0 . 7 ( A D 7 )

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E A / V P P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 8

 

 

N C

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 7

 

 

A L E /

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P R O G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 6

 

 

P S E N

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 5

 

 

P 2 . 7 ( A 1 5 )

1 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 4

 

 

P 2 . 6 ( A 1 4 )

1 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 3

 

 

P 2 . 5 ( A 1 3 )

1 21 31 41 51 61 71 81 92 02 12 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.6 P3.7 TAL2 TAL1 GND GND P2.0 P2.1 P2.2 P2.3 P2.4

 

 

 

 

 

 

 

 

 

) ) X X

 

 

) ) ) ) )

 

 

 

 

 

 

 

 

 

 

(WR

 

(RD

 

 

 

 

 

 

 

 

(A8 (A9 (A10 (A11 (A12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PDIP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 2 ) P 1 . 0

 

1

 

 

 

 

 

 

 

4 0

 

 

 

V C C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 2 E X ) P 1 . 1

 

2

 

 

 

 

 

 

 

3 9

 

 

 

P 0 . 0 ( A D 0 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 2

 

3

 

 

 

 

 

 

 

3 8

 

 

 

P 0 . 1 ( A D 1 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 3

 

4

 

 

 

 

 

 

 

3 7

 

 

 

P 0 . 2 ( A D 2 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 4

 

5

 

 

 

 

 

 

 

3 6

 

 

 

P 0 . 3 ( A D 3 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 5

 

6

 

 

 

 

 

 

 

3 5

 

 

P 0 . 4 ( A D 4 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 6

 

7

 

 

 

 

 

 

 

3 4

 

 

P 0 . 5 ( A D 5 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 7

 

8

 

 

 

 

 

 

 

3 3

 

 

P 0 . 6 ( A D 6 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R S T

 

9

 

 

 

 

 

 

 

3 2

 

 

P 0 . 7 ( A D 7 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( R X D ) P 3 . 0

 

1 0

 

 

 

 

 

 

3 1

 

 

 

E A

/ V P P

 

 

 

 

 

 

 

 

 

 

 

 

 

( T X D ) P 3 . 1

 

1 1

 

 

 

 

 

 

3 0

 

 

A L E /

P R O G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 9

 

 

 

 

 

 

 

 

 

 

 

 

(

 

I N T 0

) P 3 . 2

 

1 2

 

 

 

 

 

 

 

 

 

P S E N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(

 

 

 

 

1 3

 

 

 

 

 

 

2 8

 

 

P 2 . 7 ( A 1 5 )

 

 

I N T 1 ) P 3 . 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 0 ) P 3 . 4

 

1 4

 

 

 

 

 

 

2 7

 

 

P 2 . 6 ( A 1 4 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 1 ) P 3 . 5

 

1 5

 

 

 

 

 

 

2 6

 

 

 

P 2 . 5 ( A 1 3 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 5

 

 

P 2 . 4 ( A 1 2 )

 

 

 

 

( W R ) P 3 . 6

 

1 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 4

 

 

 

 

 

 

 

 

( R D ) P 3 . 7

 

1 7

 

 

 

 

 

 

 

 

 

P 2 . 3 ( A 1 1 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X TA L 2

 

1 8

 

 

 

 

 

 

2 3

 

 

 

P 2 . 2 ( A 1 0 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X TA L 1

 

1 9

 

 

 

 

 

 

2 2

 

 

 

P 2 . 1 ( A 9 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G N D

 

2 0

 

 

 

 

 

 

2 1

 

 

 

P 2 . 0 ( A 8 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PLCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2 EX) 2)

 

 

 

 

D0) D1) D2) D3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(T (T

 

 

 

 

(A (A (A (A

 

 

 

 

 

 

I N D E X

 

.1P4

.1P3 .1P2 .1P1 .1P0

CN

VCC P0.0 P0.1 P0.2 P0.3

 

 

 

 

 

 

C O R N E R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

4

 

 

 

2

4 4

 

 

4 2

4 0

 

 

 

 

 

 

 

 

 

 

 

 

 

P 1 . 5

 

7

5

 

 

3

 

 

1

4 3 4 13 9

 

 

P 0 . 4 ( A D 4 )

 

 

 

 

 

 

 

P 1 . 6

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 8

 

 

P 0 . 5 ( A D 5 )

 

 

 

 

 

 

 

P 1 . 7

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 7

 

 

P 0 . 6 ( A D 6 )

 

 

 

 

 

 

 

R S T

 

1 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 6

 

 

P 0 . 7 ( A D 7 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( R X D ) P 3 . 0

 

1 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 5

 

 

 

E A

/ V P P

 

 

 

 

 

 

 

 

 

N C

 

1 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 4

 

 

N C

( T X D ) P 3 . 1

 

1 3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 3

 

 

A L E / P R O G

(

 

 

 

 

 

 

) P 3 . 2

 

1 4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 2

 

 

P S E N

I N T 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(

 

 

 

 

) P 3 . 3

 

1 5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 1

 

 

P 2 . 7 ( A 1 5 )

I N T 1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 0 ) P 3 . 4

 

1 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3 0

 

 

P 2 . 6 ( A 1 4 )

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

( T 1 ) P 3 . 5

 

1 7

1 9 2 1

 

2 3

2 5 2 72 9

 

 

P 2 . 5 ( A 1 3 )

 

 

 

 

 

 

 

 

 

 

1 8

2 0

2 2

2 4

 

2 6

2 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P3.6 P3.7 TAL2 TAL1 GND NC P2.0 P2.1 P2.2 P2.3 P2.4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(WR) (RD) X X

 

 

(A8) (A9) (A10) (A11) (A12)

 

 

 

 

8-Bit Microcontroller with 8K Bytes QuickFlash

AT87F52

Rev. 1011A–02/98

1

ATMEL AT87F52-24PI, AT87F52-24PC, AT87F52-24JI, AT87F52-24JC, AT87F52-24AI Datasheet

Block Diagram

 

 

 

 

 

 

 

 

 

P0.0

- P0.7

P2.0

- P2.7

 

VCC

 

 

 

 

 

 

 

 

 

 

PORT 0 DRIVERS

PORT 2 DRIVERS

 

GND

 

 

 

 

 

 

 

 

RAM ADDR.

RAM

PORT 0

PORT 2

QUICK

 

 

REGISTER

LATCH

LATCH

FLASH

 

 

 

 

 

B

 

 

 

STACK

PROGRAM

 

ACC

 

 

ADDRESS

 

REGISTER

 

 

POINTER

 

 

 

 

REGISTER

 

 

 

 

 

 

 

 

 

 

TMP2

TMP1

 

 

BUFFER

 

 

 

 

 

 

 

 

 

 

 

 

 

PC

 

 

 

ALU

 

 

 

INCREMENTER

 

 

 

 

INTERRUPT, SERIAL PORT,

 

 

 

 

 

 

AND TIMER BLOCKS

 

 

 

 

 

 

 

 

PROGRAM

 

 

 

PSW

 

 

 

COUNTER

 

 

 

 

 

 

 

PSEN

 

 

 

 

 

 

 

ALE/PROG

TIMING

INSTRUCTION

 

 

 

 

DPTR

AND

 

 

 

 

 

 

 

 

 

 

REGISTER

 

 

 

 

EA / VPP

CONTROL

 

 

 

 

 

 

 

 

 

 

 

RST

 

 

 

 

 

 

 

 

 

 

PORT 1

PORT 3

 

 

 

 

LATCH

 

LATCH

 

 

OSC

 

 

 

 

 

 

 

 

 

PORT 1 DRIVERS

PORT 3 DRIVERS

 

 

 

 

P1.0 - P1.7

P3.0

- P3.7

 

 

 

 

 

 

 

2

 

AT87F52

 

 

 

 

The AT87F52 provides the following standard features: 8K bytes of QuickFlash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT87F52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.

Port 0 also receives the code bytes during QuickFlash programming and outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.

Port 1 also receives the low-order address bytes during QuickFlash programming and verification.

Port Pin

Alternate Functions

 

 

P1.0

T2 (external count input to Timer/Counter 2),

 

clock-out

 

 

P1.1

T2EX (Timer/Counter 2 capture/reload trigger

 

and direction control)

 

 

 

 

 

 

 

 

 

AT87F52

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during QuickFlash programming and verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.

Port 3 also receives some control signals for QuickFlash programming and verification.

Port Pin

Alternate Functions

 

 

 

P3.0

 

RXD (serial input port)

 

 

 

P3.1

 

TXD (serial output port)

 

 

 

 

 

 

P3.2

 

 

 

 

(external interrupt 0)

 

INT0

 

 

 

 

 

 

P3.3

 

 

 

 

(external interrupt 1)

 

INT1

 

 

 

P3.4

 

T0 (timer 0 external input)

 

 

 

P3.5

 

T1 (timer 1 external input)

 

 

 

 

 

P3.6

 

 

 

(external data memory write strobe)

 

WR

 

 

 

 

P3.7

 

 

(external data memory read strobe)

RD

 

 

 

 

 

 

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE/PROG

Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during QuickFlash programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE

3

pulse is skipped during each access to external data memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

Program Store Enable is the read strobe to external program memory.

When the AT87F52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.

This pin also receives the 12-volt programming enable voltage (VPP) during QuickFlash programming.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Table 1. AT87F52 SFR Map and Reset Values

0F8H

 

 

 

 

 

 

 

 

0FFH

 

 

 

 

 

 

 

 

 

 

0F0H

B

 

 

 

 

 

 

 

0F7H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E8H

 

 

 

 

 

 

 

 

0EFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0E0H

ACC

 

 

 

 

 

 

 

0E7H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D8H

 

 

 

 

 

 

 

 

0DFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0D0H

PSW

 

 

 

 

 

 

 

0D7H

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0C8H

T2CON

T2MOD

RCAP2L

RCAP2H

TL2

TH2

 

 

0CFH

00000000

XXXXXX00

00000000

00000000

00000000

00000000

 

 

 

 

 

 

0C0H

 

 

 

 

 

 

 

 

0C7H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B8H

IP

 

 

 

 

 

 

 

0BFH

XX000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0B0H

P3

 

 

 

 

 

 

 

0B7H

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0A8H

IE

 

 

 

 

 

 

 

0AFH

0X000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0A0H

P2

 

 

 

 

 

 

 

0A7H

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

98H

SCON

SBUF

 

 

 

 

 

 

9FH

00000000

XXXXXXXX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

90H

P1

 

 

 

 

 

 

 

97H

11111111

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

88H

TCON

TMOD

TL0

TL1

TH0

TH1

 

 

8FH

00000000

00000000

00000000

00000000

00000000

00000000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

80H

P0

SP

DPL

DPH

 

 

 

PCON

87H

11111111

00000111

00000000

00000000

 

 

 

0XXX0000

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

AT87F52

 

 

 

AT87F52

Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke

Table 2. T2CON—Timer/Counter 2 Control Register

new features. In that case, the reset or inactive values of the new bits will always be 0.

Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.

 

 

T2CON Address = 0C8H

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value = 0000 0000B

 

 

Bit Addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

TF2

 

EXF2

 

RCLK

 

TCLK

EXEN2

 

TR2

 

C/T2

 

 

CP/RL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

6

 

5

 

4

3

2

 

1

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF2

 

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either

 

 

 

 

 

 

RCLK = 1 or TCLK = 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXF2

 

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =

 

 

 

 

 

 

1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2

 

 

 

 

 

 

must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

 

 

 

RCLK

 

Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial

 

 

 

 

 

 

port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

 

 

 

 

 

 

 

 

 

TCLK

 

Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial

 

 

 

 

 

 

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

 

 

 

 

 

 

 

 

 

EXEN2

 

Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX

 

 

 

 

 

 

if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TR2

 

Start/Stop control for Timer 2. TR2 = 1 starts the timer.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T2

 

 

 

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge

 

 

 

 

 

 

triggered).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP/RL2

 

Capture/Reload select. CP/RL2

= 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2

 

 

 

 

 

 

= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2

 

 

 

 

 

 

= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Memory

The AT87F52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.

When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.

For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.

5

Timer 0 and 1

Timer 0 and Timer 1 in the AT87F52 operate the same way as Timer 0 and Timer 1 in the AT87F51.

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

Table 3. Timer 2 Operating Modes

 

 

 

 

 

 

RCLK +TCLK

CP/RL2

TR2

MODE

 

 

 

 

 

 

0

0

 

1

16-Bit Auto-Reload

 

 

 

 

 

 

0

1

 

1

16-Bit Capture

 

 

 

 

 

 

1

X

1

Baud Rate Generator

 

 

 

 

 

 

X

X

0

(Off)

 

 

 

 

 

 

In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples

Figure 1. Timer in Capture Mode

show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1- to-0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 1.

Auto-Reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 4). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.

OSC ÷12

C/T2 = 0

TH2

TL2

 

 

TF2

 

 

 

 

 

 

 

 

 

 

OVERFLOW

CONTROL

TR2

C/T2 = 1

T2 PIN

CAPTURE

 

RCAP2H RCAP2L

TRANSITION

DETECTOR TIMER 2 INTERRUPT

T2EX PIN

EXF2

CONTROL

EXEN2

6

AT87F52

 

 

 

AT87F52

Figure 2 shows Timer 2 automatically counting up when DCEN = 0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 3. In this mode, the T2EX pin controls

the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

 

OSC

 

 

 

 

 

÷12

 

 

C/T2 = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TH2

 

 

TL2

 

 

OVERFLOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C/T2 = 1

 

TR2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RELOAD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER 2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2 PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RCAP2H

 

RCAP2L

 

 

 

 

 

 

 

INTERRUPT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TRANSITION

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TF2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DETECTOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2EX PIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXF2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EXEN2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 4. T2MOD—Timer 2 Mode Control Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2MOD Address = 0C9H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset Value = XXXX XX00B

Not Bit Addressable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2OE

 

 

 

DCEN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

 

 

7

 

 

 

6

 

5

 

 

 

 

4

 

 

 

 

 

 

3

 

 

 

 

 

 

2

 

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Symbol

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Not implemented, reserved for future

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T2OE

 

 

Timer 2 Output Enable bit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DCEN

 

 

When set, this bit allows Timer 2 to be configured as an up/down counter.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

Loading...
+ 15 hidden pages