ATMEL AT80F52-12AI, AT80F52-12AC, AT80F52-20PI, AT80F52-20PC, AT80F52-20JI Datasheet

...
0 (0)
3-15
PLCC
P1.0 (T2)
VCC
P1.1 (T2 EX)
P0.0 (AD0)
P1.2
ALE
XTAL1
EA
(WR) P3.6
GND
(RXD) P3.0
P0.7 (AD7)
P2.6 (A14)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3 (AD3)
P0.2 (AD2)
P1.3
P0.1 (AD1)
PSEN
XTAL2
(INT0) P3.2
(TXD) P3.1
(T1) P3.5
(INT1) P3.3
(T0) P3.4
P2.7 (A15)
(A11) P2.3
(A12) P2.4
(A10) P2.2
(A9) P2.1
(A8) P2.0
NC
23
1
RST
INDEX
CORNER
NC
NC
P2.5 (A13)
34
NC
42
43
40
41
6
5
444
3
2
26
25
28
27
18
19
20 24
21
22
7
8
9
10
11
12
13
14
15
16
17 29
30
39
38
37
36
35
33
32
31
P1.4
P1.5
P1.6
P1.7
Features
Compatible with MCS-51™ Products
8K Bytes of Factory Programmable QuickFlash
Memory
Fully Static Operation: 0 Hz to 20 MHz
Three-Level Program Memory Lock
256 x 8-Bit Internal RAM
32 Programmable I/O Lines
Three 16-Bit Timer/Counters
Eight Interrupt Sources
Programmable Serial Channel
Low Power Idle and Power Down Modes
Description
The AT80F52 is a low-power, high-performance CMOS 8-bit microcomputer with 8K
bytes of Qui ckF lash memo ry. The dev ice i s m anuf actu red u sin g A tmel ’s hi gh d ens ity
nonvolatile memory technology and is compatib le with the indu stry standard 80C51
and 80C52 instruction set and pinout. The on-chip QuickFlash allows custom codes to
be quickly programmed in the factory. B y co mbi nin g a v ersa til e 8-bit CPU with Quick-
Flash on a monolithic chip, the Atmel AT80F52 is a powerful microcomputer which
provides a highly flex ible and co st effe ctive solu tion to many embedd ed con trol app li-
cations.
0980A-A–12/97
8-Bit
Microcontroller
with 8K Bytes
Quic kFlash
Memory
AT80F52
PDIP
(T2) P1.0
V
CC
(T2 EX) P1.1
P0.0 (AD0)
P1.2
(INT0) P3.2
ALE
(RD) P3.7 P2.3 (A11)
(TXD) P3.1
EA
(WR) P3.6
P2.4 (A12)
(RXD) P3.0
P0.7 (AD7)
(T1) P3.5
P2.6 (A14)
RST
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3 (AD3)
P0.2 (AD2)
P1.3
P0.1 (AD1)
(INT1) P3.3
PSEN
XTAL2 P2.2 (A10)
(T0) P3.4
P2.7 (A15)
XTAL1 P2.1 (A9)
GND P2.0 (A8)
P2.5 (A13)
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
21
22
23
24
25
26
40
39
38
37
36
35
34
33
32
31
30
29
28
27
P1.4
P1.5
P1.6
P1.7
Pin Configurations
TQFP
23
1
INDEX
CORNER
34
P1.0 (T2)
VCC
P1.1 (T2 EX)
P1.2
P1.3
NC
42
43
40
41
6
5
4
44
3
2
26
25
28
27
24
18
19
20
21
22
NC
7
8
9
10
11
12
13
14
15
16
17
29
30
39
38
37
36
35
33
32
31
NC
PSEN
XTAL1
GND
XTAL2
GND
P0.0 (AD0)
ALE
(RD) P3.7
EA
(WR) P3.6
(RXD) P3.0
P0.7 (AD7)
P2.6 (A14)
P0.6 (AD6)
P0.5 (AD5)
P0.4 (AD4)
P0.3 (AD3)
P0.2 (AD2)
P0.1 (AD1)
(INT0) P3.2
(TXD) P3.1
(T1) P3.5
(INT1) P3.3
(T0) P3.4
P2.7 (A15)
(A11) P2.3
(A12) P2.4
(A10) P2.2
(A9) P2.1
(A8) P2.0
RST
P2.5 (A13)
P1.4
P1.5
P1.6
P1.7
(continued)
AT80F52
3-16
Block Diagram
PORT 2 DRIVERS
PORT 2
LATCH
P2.0 - P2.7
QUICK
FLASH
PORT 0
LATCH
RAM
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
RAM ADDR.
REGISTER
INSTRUCTION
REGISTER
B
REGISTER
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
STACK
POINTER
ACC
TMP2
TMP1
ALU
PSW
TIMING
AND
CONTROL
PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
OSC
GND
V
CC
PSEN
ALE
EA
RST
PORT 0 DRIVERS
P0.0 - P0.7
AT80F52
3-17
The AT80F52 provides the following standard features: 8K
bytes of QuickF lash, 25 6 bytes of RAM, 32 I/ O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi-
tecture, a full duplex serial port, on-chip os cillator, and
clock circuitry. In addition, the AT80F52 is designed with
static logic for operation down to zero frequency and sup-
ports two softwar e selectable po wer saving modes . The
Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial p or t, and int er rupt s yst em to co nti nue
functioning. The Power Down Mode saves the RAM con-
tents but freezes the oscillator, disabling all other chip func-
tions until the next hardware reset.
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 0
Port 0 is an 8-bit open drain bidirectional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high-
impedance inputs.
Port 0 can also be configu red to be the multiplex ed low-
order address/data bus during accesses to ex ternal pro-
gram and data memory. In this mode, P0 has internal pul-
lups.
Port 0 also out puts the c ode b yt es d uring p ro gram verifica-
tion. External pu llups are requ ired dur ing pro gram ver ifica-
tion.
Port 1
Port 1 is an 8-bit bidire ction al I/O por t w ith inter nal pullu ps.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins , they are p ulled hi gh by
the internal pullups and can be used as inputs. As inputs ,
Port 1 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
In addition, P1.0 and P1. 1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.
Port 1 also receives the low-order address bytes during
QuickFlash verification.
Port 2
Port 2 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 2 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I
IL
) because of the internal pullups.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory th at u se 16 -b it a ddres s es ( MO VX @
DPTR). In this application, Port 2 uses strong internal pul-
lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some
control signals during QuickFlash verification.
Port 3
Port 3 is an 8-bit bidirectional I/O port with interna l pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are writte n to Po rt 3 pi ns, they a re pul led high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I
IL
) because of the pullups.
Port 3 also serv es t he fun ctions of v arious spe cial f eatures
of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for QuickFlash
verification.
RST
Reset input. A high on this pin for two machine cycles while
the oscillator is running resets the device.
ALE
Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
ory.
In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim-
ing or clocking purposes. Note, however, that one ALE
pulse is skipped d ur in g ea ch ac c ess to ex ter na l d ata mem -
ory.
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter2),
clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger
and direction control)
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
(external interrupt 0)
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
(external data memory write strobe)
P3.7 RD
(external data memory read strobe)
AT80F52
3-18
If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur-
ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.
PSEN
Program Store Enable is the read strobe to external pro-
gram memory.
When the AT80F52 is executing code from external pro-
gram memory, PSEN
is activated twice each machine
cycle, except that two PSEN
activations are skipped during
each access to external data memory.
EA
External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external pro-
gram memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA
will be
internally latched on reset.
EA
should be strapped to V
CC
for internal program execu-
tions.
XTAL1
Input to the inverting oscillator am plifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
Table 1.
AT80F52 SFR Map and Reset Values
0F8H 0FFH
0F0H
B
00000000
0F7H
0E8H 0EFH
0E0H
ACC
00000000
0E7H
0D8H 0DFH
0D0H
PSW
00000000
0D7H
0C8H
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0CFH
0C0H 0C7H
0B8H
IP
XX000000
0BFH
0B0H
P3
11111111
0B7H
0A8H
IE
0X000000
0AFH
0A0H
P2
11111111
0A7H
98H
SCON
00000000
SBUF
XXXXXXXX
9FH
90H
P1
11111111
97H
88H
TCON
00000000
TMOD
00000000
TL0
00000000
TL1
00000000
TH0
00000000
TH1
00000000
8FH
80H
P0
11111111
SP
00000111
DPL
00000000
DPH
00000000
PCON
0XXX0000
87H
AT80F52
3-19
Special Function Registers
A map of the on-chip memory area called the Special Func-
tion Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted loca-
tions, since they may be used in future products to invoke
new features. In th at case, th e reset or inac tive valu es of
the new bits will always be 0.
Timer 2 Registers:
Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCA P2L )
are the Capture/ Reloa d regist ers for Timer 2 i n 16-bit c ap-
ture mode or 16-bit auto-reload mode.
Interrupt Registers:
The individual interrupt enable bits
are in the IE register. Two priorities can be set for each of
the six interrupt sources in the IP register.
Table 2.
T2CON—Timer/Counter 2 Control Register
Data Memory
The AT80F52 implements 256 bytes of on-chip RAM. The
upper 128 bytes oc cupy a parallel ad dress space to the
Special Function Register s. That means the u pper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.
When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.
For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing inst ructi on, where R0 contains 0A 0H, a cc es ses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail -
able as stack space.
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2
CP/RL2
76543210
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 =
1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2
must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial
port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Trans mit clock enable. When set, causes the serial port to use Timer 2 o v erf lo w puls es f o r its tr ansm it clock in serial
port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX
if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).
CP/RL2
Capture/Reload select. CP/RL2 = 1 causes captures to occur on neg ativ e tran sitions at T2 EX if EXEN2 = 1. CP/RL 2
= 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2
= 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
AT80F52
3-20
Timer 0 and 1
Timer 0 and Timer 1 in the AT80F52 operate the same way
as Timer 0 and Timer 1 in the AT89C51.
Timer 2
Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
in the SFR T2 C ON (sh o w n i n Ta bl e 2).
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8- bi t regi st er s, TH2 and TL2. I n the
Timer function, the TL2 r egister is incremented ever y
machine cycle. Since a machine cycle consists of 12 oscil-
lator periods, the count rate is 1/12 of the oscillator fre-
quency.
Table 3.
Timer 2 Operating Modes
In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In thi s func tion, the extern al i nput is sa mpled
during S5P2 of every machin e cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator perio ds ) ar e re qui red to recognize a 1-to -0 tr an si -
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 p er forms t he sa me operation, but a 1 -
to-0 transition at external input T2EX also causes the cur-
rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, resp ective ly. In addi tion, th e transit ion at T2E X
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus-
trated in Figure 1.
Auto-Reload (Up or Down Counter)
Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that ti mer 2 will defa ult to count u p. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-Bit Auto-Reload
0 1 1 16-Bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
Figure 1.
Timer in Capture Mode
OSC
EXF2
T2EX PIN
T2 PIN
TR2
EXEN2
C/T2 = 0
C/T2 = 1
CONTROL
CAPTURE
OVERFLOW
CONTROL
TRANSITION
DETECTOR
TIMER 2
INTERRUPT
÷12
RCAP2LRCAP2H
TH2 TL2
TF2
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