ATMEL AT80F51-20PI, AT80F51-20PC, AT80F51-20JI, AT80F51-20JC, AT80F51-20AI Datasheet

Features
• Compatible with MCS-51™ Products
• 4K Bytes of Factory Programmable QuickFlash™											Memory
• Fully Static Operation: 0 Hz to 20 MHz
• Three-Level Program Memory Lock
• 128 x 8-Bit Internal RAM
• 32 Programmable I/O Lines
•	Two 16-Bit Timer/Counters
•	Six Interrupt Sources
•	Programmable Serial Channel																			8-Bit
• Low Power Idle and Power Down Modes
Description																				Microcontroller
The AT80F51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K																				with 4K Bytes
bytes of QuickFlash Memory. The device is manufactured using Atmel’s high density
nonvolatile memory technology and is compatible with the industry standard MCS-																				QuickFlash™
51™ instruction set and pinout. The on-chip QuickFlash allows custom codes to be
quickly programmed in the factory. By combining a versatile 8-bit CPU with Quick-																				Memory
Flash on a monolithic chip, the Atmel AT80F51 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.																		(continued)		AT80F51
Pin Configurations														PDIP
											P 1 . 0			1		4 0		V C C
											P 1 . 1			2		3 9		P 0 . 0 ( A D 0 )
											P 1 . 2			3		3 8		P 0 . 1 ( A D 1 )
											P 1 . 3			4		3 7		P 0 . 2 ( A D 2 )
											P 1 . 4			5		3 6		P 0 . 3 ( A D 3 )
											P 1 . 5			6		3 5		P 0 . 4 ( A D 4 )
											P 1 . 6			7		3 4		P 0 . 5 ( A D 5 )
											P 1 . 7			8		3 3		P 0 . 6 ( A D 6 )
											R S T			9		3 2		P 0 . 7 ( A D 7 )
				TQFP							( R X D ) P 3 . 0			1 0		3 1		E A
											( T X D ) P 3 . 1			1 1		3 0		A L E
							)	) ) )			( I N T 0 ) P 3 . 2			1 2		2 9		P S E N
							D0	D1 D2 D3
											( I N T 1 ) P 3 . 3			1 3		2 8		P 2 . 7 ( A 1 5 )
	I N D E X						(A (A (A (A				( T 0 ) P 3 . 4			1 4		2 7		P 2 . 6 ( A 1 4 )
		1.4 1.3 1.2 1.1 1.0 C				CC	0.0	0.1 0.2 0.3			( T 1 ) P 3 . 5			1 5		2 6		P 2 . 5 ( A 1 3 )
	C O R N E R										( W R ) P 3 . 6			1 6		2 5		P 2 . 4 ( A 1 2 )
		P P P P P N				V	P	P P P			( R D ) P 3 . 7			1 7		2 4		P 2 . 3 ( A 1 1 )
		4 4	4 2	4 0		3 8	3 6		3 4		X TA L 2			1 8		2 3		P 2 . 2 ( A 1 0 )
											X TA L 1			1 9		2 2		P 2 . 1 ( A 9 )
		4 3		4 1	3 9		3 7	3 5
	P 1 . 5	1							3 3	P 0 . 4 ( A D 4 )	G N D			2 0		2 1		P 2 . 0 ( A 8 )
	P 1 . 6	2							3 2	P 0 . 5 ( A D 5 )				PLCC
	P 1 . 7	3							3 1	P 0 . 6 ( A D 6 )
	R S T	4							3 0	P 0 . 7 ( A D 7 )						) ) ) )
	( R X D ) P 3 . 0	5							2 9	E A						0 1 2 3
																AD AD AD AD
	N C	6							2 8	N C
	( T X D ) P 3 . 1	7							2 7	A L E						( ( ( (
											I N D E X
( I N T 0 ) P 3 . 2		8							2 6	P S E N		P1.4	P1.3 P1.2 P1.1 P1.0 NC			VCC P0.0 P0.1 P0.2 P0.3
											C O R N E R
( I N T 1 ) P 3 . 3		9							2 5	P 2 . 7 ( A 1 5 )
	( T 0 ) P 3 . 4	1 0							2 4	P 2 . 6 ( A 1 4 )
	( T 1 ) P 3 . 5	1 1							2 3	P 2 . 5 ( A 1 3 )		6		4	2 4 4 4 2 4 0
		1 3		1 5	1 7		1 9	2 0	2 1		P 1 . 5	7	5	3	1 4 3 4 13 9				P 0 . 4 ( A D 4 )
		1 2	1 4	1 6		1 8			2 2		P 1 . 6	8						3 8	P 0 . 5 ( A D 5 )
		P3.6 P3.7 TAL2 TAL1 GND GND P2.0 P2.1						P2.2 P2.3 P2.4			P 1 . 7	9						3 7	P 0 . 6 ( A D 6 )
											R S T 1 0							3 6	P 0 . 7 ( A D 7 )
											( R X D ) P 3 . 0	1 1						3 5	E A
		) ) X X				) )		) ) )			N C	1 2						3 4	N C
		(WR (RD				(A8 (A9		(A10 (A11 (A12
											( T X D ) P 3 . 1	1 3						3 3	A L E
											( I N T 0 ) P 3 . 2	1 4						3 2 P S E N
											( I N T 1 ) P 3 . 3	1 5						3 1	P 2 . 7 ( A 1 5 )
											( T 0 ) P 3 . 4	1 6						3 0	P 2 . 6 ( A 1 4 )
											( T 1 ) P 3 . 5	1 7	1 9 2 1		2 3 2 5 2 72 9				P 2 . 5 ( A 1 3 )
												1 8		2 0	2 2	2 4	2 6	2 8
												P3.6 P3.7 TAL2 TAL1 GND NC P2.0 P2.1 P2.2 P2.3 P2.4
												(WR)	(RD) X X			(A8) (A9)	(A10) (A11) (A12)			0979A-A–12/97
																				3-3

Block Diagram
			P0.0	- P0.7	P2.0	-	P2.7
VCC
			PORT 0 DRIVERS		PORT 2 DRIVERS
GND
	RAM ADDR.		RAM	PORT 0	PORT 2		QUICK
	REGISTER			LATCH	LATCH		FLASH
	B				STACK			PROGRAM
		ACC						ADDRESS
	REGISTER				POINTER
								REGISTER
			TMP2	TMP1				BUFFER
								PC
			ALU					INCREMENTER
				INTERRUPT, SERIAL PORT,
					AND TIMER BLOCKS
								PROGRAM
			PSW					COUNTER
PSEN
ALE	TIMING	INSTRUCTION						DPTR
	AND
		REGISTER
EA	CONTROL
RST
			PORT 1		PORT 3
			LATCH		LATCH
	OSC
			PORT 1 DRIVERS		PORT 3 DRIVERS
			P1.0 - P1.7		P3.0	- P3.7
3-4		AT80F51

The AT80F51 provides the following standard features: 4K bytes of QuickFlash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT80F51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle M od e s to p s t he C P U w hi l e a l l ow i ng t he R A M , timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.

Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups.

Port 0 also outputs the code bytes during program verification. External pullups are required during program verification.

Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during QuickFlash verification.

Port 2

Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data mem-

AT80F51

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some control signals during QuickFlash verification.

Port 3

Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Port 3 also serves the functions of various special features of the AT80F51 as listed below:

Port Pin	Alternate Functions
P3.0		RXD (serial input port)
P3.1		TXD (serial output port)
P3.2						(external interrupt 0)
		INT0
P3.3						(external interrupt 1)
		INT1
P3.4		T0 (timer 0 external input)
P3.5		T1 (timer 1 external input)
P3.6				(external data memory write strobe)
		WR
P3.7			(external data memory read strobe)
		RD

Port 3 also receives some control signals for QuickFlash verification.

RST

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device.

ALE

Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory.

In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external program memory.

When the AT80F51 is executing code from external program memory, PSEN is activated twice each machine

3-5

cycle, except that two PSEN activations are skipped during each access to external data memory.

EA

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.

EA should be strapped to VCC for internal program executions.

XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

Figure 1. Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 2. External Clock Drive Configuration

Idle Mode

In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of

Power Down Mode

In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is termi-

Status of External Pins During Idle and Power Down Modes

Mode	Program Memory	ALE	PSEN			PORT0	PORT1	PORT2	PORT3
Idle	Internal	1	1			Data	Data	Data	Data
Idle	External	1	1			Float	Data	Address	Data
Power Down	Internal	0	0			Data	Data	Data	Data
Power Down	External	0	0			Float	Data	Data	Data

3-6	AT80F51