ATMEL AT6003-4QI, AT6003-4QC, AT6003-4JI, AT6003-4JC, AT6003-4AI Datasheet

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AT6000/LV Series

Features

High Performance

System Speeds > 100 MHz Flip-Flop Toggle Rates > 250 MHz 1.2 ns/1.5 ns Input Delay

3.0ns/6.0 ns Output Delay

Up to 204 User I/Os

Thousands of Registers

Cache Logic®Design

Complete/Partial In-System Reconfiguration No Loss of Data or Machine State

Adaptive Hardware

Low Voltage and Standard Voltage Operation

5.0 (VCC = 4.75V to 5.25V)

3.3(VCC = 3.0V to 3.6V)

Automatic Component Generators Reusable Custom Hard Macro Functions

Very Low Power Consumption

Standby Current of 500 μA/ 200 μA

Programmable Clock Options Independently Controlled Column Clocks Independently Controlled Column Resets Clock Skew Less Than 1 ns Across Chip

Independently Configurable I/O (PCI Compatible)Typical Operating Current of 15 to 170 mA

 

TTL/CMOS Input Thresholds

 

Open Collector/Tri-state Outputs

 

Programmable Slew-Rate Control

I/O Drive of 16 mA (combinable to 64 mA)

Easy Migration to Atmel Gate Arrays for High Volume Production

Description

AT6000 Series SRAM-Based Field Programmable Gate Arrays (FPGAs) are ideal for use as reconfigurable coprocessors and implementing compute intensive logic.

Supporting system speeds greater than 100 MHz and using a typical operating current of 15 to 170 mA, AT6000 Series devices are ideal for high-speed, compute-intensive designs. These FPGAs are designed to implement Cache Logic®, which provides the user with the ability to implement adaptive hardware and perform hardware acceleration.

The patented AT6000 Series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable

I/O.

(continued)

AT6000 Series Field Programmable Gate Arrays

Device

AT6002

AT6003

AT6005

AT6010

Usable Gates

6,000

9,000

15,000

30,000

Cells

1,024

1,600

3,136

6,400

 

 

 

 

 

Registers (maximum)

1,024

1,600

3,136

6,400

 

 

 

 

 

I/O (maximum)

96

120

108

204

Typ. Operating Current (mA)

15-30

25-45

40-80

85-170

 

 

 

 

 

Cell Rows x Columns

32 x 32

40 x 40

56 x 56

80 x 80

 

 

 

 

 

Coprocessor

Field

Programmable

Gate Arrays

0264E

2-3

ATMEL AT6003-4QI, AT6003-4QC, AT6003-4JI, AT6003-4JC, AT6003-4AI Datasheet

Description (Continued)

Devices range in size from 4,000 to 30,000 usable gates, and 1024 to 6400 registers. Pin locations are consistent throughout the AT6000 Series for easy design migration. High-I/O versions are available for the lower gate count devices.

AT6000 Series FPGAs utilize a reliable 0.6 μm singlepoly, double-metal CMOS process and are 100% factorytested.

Atmel’s PCand workstation-based Integrated Development System is used to create AT6000 Series designs. Multiple design entry methods are supported.

The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, very efficient and contain the most important and most commonly used logic and wiring functions. The cell’s small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances.

Figure 1. Symmetrical Array Surrounded by I/O

The Symmetrical Array

At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous and completely uninterrupted from one edge to the other, except for bus repeaters spaced every eight cells (Figure 2).

In addition to logic and storage, cells can also be used as wires to connect functions together over short distances and are useful for routing in tight spaces.

The Busing Network

There are two kinds of buses: local and express (see Figures 2 and 3).

Local buses are the link between the array of cells and the busing network. There are two local buses— North-South 1 and 2 (NS1 and NS2)— for every column of cells, and two local buses— East-West 1 and 2 (EW1 and EW2)— for every row of cells. In a sector (an 8 x 8 array of cells enclosed by repeaters) each local bus is connected to every cell in its column or row, thus providing every cell in

(continued)

2-4 AT6000/LV Series

AT6000/LV Series

Figure 2. Busing Network (one sector)

CELL

REPEATER

Figure 3. Cell-to-Cell and Bus-to-Bus Connections

2-5

Description (Continued)

the array with read/write access to two North-South and two East-West buses.

Each cell, in addition, provides the ability to route a signal on a 90° turn between the NS1 bus and EW1 bus and between the NS2 bus and EW2 bus.

Express buses are not connected directly to cells, and thus provide higher speeds. They are the fastest way to cover long, straight-line distances within the array.

Each express bus is paired with a local bus, so there are two express buses for every column and two express buses for every row of cells.

Connective units, called repeaters, spaced every eight cells, divide each bus, both local and express, into segments spanning eight cells. Repeaters are aligned in rows and columns thereby partitioning the array into 8 x 8 sectors of cells. Each repeater is associated with a local/express pair, and on each side of the repeater are connections to a local-bus segment and an express-bus segment. The repeater can be programmed to provide any one of twenty-one connecting functions. These functions are symmetric with respect to both the two repeater sides and the two types of buses.

Among the functions provided are the ability to:

Isolate bus segments from one another

Connect two local-bus segments

Connect two express-bus segments

Implement a local/express transfer

In all of these cases, each connection provides signal regeneration and is thus unidirectional. For bidirectional connections, the basic repeater function for the NS2 and EW2 repeaters is augmented with a special programmable connection allowing bidirectional communication between local-bus segments. This option is primarily used to implement long, tri-state buses.

Figure 4. Cell Structure

2-6 AT6000/LV Series

The Cell Structure

The Atmel cell (Figure 4) is simple and small and yet can be programmed to perform all the logic and wiring functions needed to implement any digital circuit. Its four sides are functionally identical, so each cell is completely symmetrical.

Read/write access to the four local buses— NS1, EW1, NS2 and EW2— is controlled, in part, by four bidirectional pass gates connected directly to the buses. To read a local bus, the pass gate for that bus is turned on and the three-input multiplexer is set accordingly. To write to a local bus, the pass gate for that bus and the pass gate for the associated tri-state driver are both turned on. The twoinput multiplexer supplying the control signal to the drivers permits either: (1) active drive, or (2) dynamic tri-stating controlled by the B input. Turning between LNS1 and LEW1 or between LNS2 and LEW2 is accomplished by turning on the two associated pass gates. The operations of reading, writing and turning are subject to the restriction that each bus can be involved in no more than a single operation.

In addition to the four local-bus connections, a cell receives two inputs and provides two outputs to each of its North (N), South (S), East (E) and West (W) neighbors. These inputs and outputs are divided into two classes: “A” and “B.” There is an A input and a B input from each neighboring cell and an A output and a B output driving all four neighbors. Between cells, an A output is always connected to an A input and a B output to a B input.

Within the cell, the four A inputs and the four B inputs enter two separate, independently configurable multiplexers. Cell flexibility is enhanced by allowing each multiplexer to select also the logical constant “1.” The two multiplexer outputs enter the two upstream AND gates.

Downstream from these two AND gates are an ExclusiveOR (XOR) gate, a register, an AND gate, an inverter and two four-input multiplexers producing the A and B outputs. These multiplexers are controlled in tandem (unlike the A and B input multiplexers) and determine the function of the cell.

In State 0— corresponding to the “0" inputs of the multiplexers— the output of the left-hand upstream AND gate is connected to the cell’s A output, and the output of the right-hand upstream AND gate is connected to the cell’s B output.

In State 1— corresponding to the “1" inputs of the multiplexers— the output of the left-hand upstream AND gate is connected to the cell’s B output, the output of the right-hand upstream AND gate is connected to the cell’s A output.

In State 2— corresponding to the “2" inputs of the multiplexers— the XOR of the outputs from the two upstream AND gates is provided to the cell’s A output,

(continued)

Figure 5a. Combinatorial Physical States

Li

 

Li

A

Li

 

 

 

B

A, Lo

B A, Lo

B A, Lo

B A, Lo

 

B

A, Lo

B

A Li

B A Li

B

A Li

A Li

 

A Li

 

A, Lo

B

 

 

A, Lo

B

 

 

A, Lo

B

 

 

 

 

 

 

 

 

A, Lo

B

 

A, Lo

 

B

 

 

 

 

 

 

 

 

 

 

 

 

Li

B

Li B Li B

A Li

 

 

A Li

B

A, Lo

B

 

 

A, Lo

A, Lo

 

 

A, Lo

B

 

 

 

 

 

 

 

 

A, Lo

B

 

 

 

 

 

 

 

A Li

B

A

B Li

B A Li

 

B

A Li

B

 

 

 

 

 

 

 

 

1

0

 

 

 

 

 

 

 

 

 

A, Lo

 

A, Lo

B

A, Lo

B

A, Lo

B

 

 

 

 

 

 

 

 

A, Lo

B

 

 

 

 

 

 

 

 

 

 

 

Figure 5b. Register States

Li

 

 

 

 

 

A

 

 

A

 

 

 

 

 

B

D

"0"

 

 

 

 

 

 

 

 

 

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A, Lo

B

 

D

 

D

 

 

D

 

 

 

 

 

Q

 

Q

 

 

Q

 

 

 

 

A, Lo

B

A, Lo

B

 

A, Lo

B

A Li

 

 

Li

B

A Li

 

 

 

 

 

 

 

 

 

D

D

 

 

 

 

 

 

 

 

Q

 

 

 

 

 

 

 

 

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

 

 

A, Lo

A, Lo

 

 

 

 

 

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A, Lo

B

 

 

 

 

 

 

 

 

 

A

B

 

Li

B

A Li

B

 

A Li

B

 

 

 

 

 

 

 

 

1

0

 

D

 

 

 

 

 

 

 

D

 

 

 

 

D

 

 

 

 

Q

 

Q

 

 

Q

 

D

 

 

A, Lo

 

 

 

 

 

 

 

 

 

A, Lo

B

A, Lo

B

Q

 

 

 

 

 

 

 

 

 

 

 

A, Lo B

AT6000/LV Series

Figure 5c.

Physical Constants

 

 

 

 

 

 

"0"

"0"

"0"

"1"

"1"

"0"

"1"

"1"

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A, Lo

B

A, Lo

B

A, Lo

B

A, Lo

B

Figure 6a. Two-Input AND Feeding XOR

A Li B

A

Figure 6b. Cell Configuration (AL) XOR B

2-7

Description (Continued)

while the NAND of these two outputs is provided to the cell’s B output.

In State 3— corresponding to the “3" inputs of the multiplexers— the XOR function of State 2 is provided to the D input of a D-type flip-flop, the Q output of which is connected to the cell’s A output. Clock and asynchronous reset signals are supplied externally as described later. The AND of the outputs from the two upstream AND gates is provided to the cell’s B output.

Logic States

The Atmel cell implements a rich and powerful set of logic functions, stemming from 44 logical cell states which permutate into 72 physical states. Some states use both A and B inputs. Other states are created by selecting the “1" input on either or both of the input multiplexers.

There are 28 combinatorial primitives created from the cell’s tri-state capabilities and the 20 physical states represented in the Figure 5a. Five logical primitives are derived from the physical constants shown in Figure 5c. More complex functions are created by using cells in combination.

A two-input AND feeding an XOR (Figure 6a) is produced using a single cell (Figure 6b). A two-to-one multiplexer selects the logical constant “0" and feeds it to the righthand AND gate. The AND gate acts as a feed-through, letting the B input pass through to the XOR. The three-to- one multiplexer on the right side selects the local-bus input, LNS1, and passes it to the left-hand AND gate. The A and LNS1 signals are the inputs to the AND gate. The output of the AND gate feeds into the XOR, producing the logic state (AL) XOR B.

Figure 7. Column Clock and Column Reset

GLOBAL

 

GLOBAL

CLOCK

 

CLOCK

"1"

 

 

A

 

 

D

 

 

Q

 

 

CELL

 

EXPRESS

EXPRESS

 

BUS

 

BUS

D

 

 

Q

 

 

CELL

 

 

D

 

R

E

B

D

U

O

I

R

U

C

I

T

A

E

I

T

D

N

E

 

G

D

 

 

CELL

 

 

D

 

 

Q

 

 

EXPRESS

 

EXPRESS

BUS

 

BUS

CELL

 

 

D

 

 

Q

 

 

A

 

 

"1"

 

 

GLOBAL

 

GLOBAL

RESET

 

RESET

Clock Distribution

Along the top edge of the array is logic for distributing clock signals to the D flip-flop in each logic cell (Figure 7). The distribution network is organized by column and permits columns of cells to be independently clocked. At the head of each column is a user-configurable multiplexer providing the clock signal for that column. It has four inputs:

Global clock supplied through the CLOCK pin

Express bus adjacent to the distribution logic

“A” output of the cell at the head of the column

Logical constant “1" to conserve power (no clock)

Through the global clock, the network provides low-skew distribution of an externally supplied clock to any or all of the columns of the array. The global clock pin is also connected directly to the array via the A input of the upper left and right corner cells (AW on the left, and AN on the right). The express bus is useful in distributing a secondary clock to multiple columns when the global clock line is used as a primary clock. The A output of a cell is useful in providing a clock signal to a single column. The constant “1" is used to reduce power dissipation in columns using no registers.

Asynchronous Reset

Along the bottom edge of the array is logic for asynchronously resetting the D flip-flops in the logic cells (Figure 7). Like the clock network, the asynchronous reset network is organized by column and permits columns to be independently reset. At the bottom of each column is a userconfigurable multiplexer providing the reset signal for that column. It has four inputs:

Global asynchronous reset supplied through the RESET pin

Express bus adjacent to the distribution logic

“A” output of the cell at the foot of the column

Logical constant “1"to conserve power

The asynchronous reset logic uses these four inputs in the same way that the clock distribution logic does. Through the global asynchronous reset, any or all columns can be reset by an externally supplied signal. The global asynchronous reset pin is also connected directly to the array via the A input of the lower left and right corner cells (AS on the left, and AE on the right). The express bus can be used to distribute a secondary reset to multiple columns when the global reset line is used as a primary reset, the A output of a cell can also provide an asynchronous reset signal to a single column, and the constant “1" is used by columns with registers requiring no reset. All registers are reset during power-up.

(continued)

2-8 AT6000/LV Series

Description (Continued)

Input/Output

The Atmel architecture provides a flexible interface between the logic array, the configuration control logic and the I/O pins.

Two adjacent cells— an “exit” and an “entrance” cell— on the perimeter of the logic array are associated with each I/O pin.

There are two types of I/Os: A-type (Figure 8a) and B-type (Figure 8b). For A-type I/Os, the edge-facing A output of an exit cell is connected to an output driver, and the edgefacing A input of the adjacent entrance cell is connected to an input buffer. The output of the output driver and the input of the input buffer are connected to a common pin.

B-type I/Os are the same as A-type I/Os, but use the B inputs and outputs of their respective entrance and exit cells. A- and B-type I/Os alternate around the array.

Control of the I/O logic is provided by user-configurable memory bits.

TTL/CMOS Inputs

A user-configurable bit determines the threshold level— TTL or CMOS— of the input buffer.

Open Collector/Tri-state Outputs

A user-configurable bit which enables or disables the active pull-up of the output device.

Slew Rate Control

A user-configurable bit controls the slew rate— fast or slow— of the output buffer. A slow slew rate, which reduces noise and ground bounce, is recommended for out-

Figure 8a. A-Type I/O Logic

AT6000/LV Series

puts that are not speed-critical. Fast and slow slew rates have the same DC-current sinking capabilities, but the rate at which each allows the output devices to reach full drive differs.

Pull-up

A user-configurable bit controls the pull-up transistor in the I/O pin. It’s primary function is to provide a logical “1" to unused input pins. When on, it is approximately equivalent to a 25K resistor to VCC.

Enable Select

User-configurable bits determine the output-enable for the output driver. The output driver can be static - - always on or always off - - or dynamically controlled by a signal generated in the array. Four options are available from the array: (1) the control is low and always driving; (2) the control is high and never driving; (3) the control is connected to a vertical local bus associated with the output cell; or (4) the control is connected to a horizontal local bus associated with the output cell. On power-up, the user I/Os are configured as inputs with pull-up resistors.

In addition to the functionality provided by the I/O logic, the entrance and exit cells provide the ability to register both inputs and outputs. Also, these perimeter cells (unlike interior cells) are connected directly to express buses: the edge-facing A and B outputs of the entrance cell are connected to express buses, as are the edge-facing A and B inputs of the exit cell. These buses are perpendicular to the edge, and provide a rapid means of bringing I/O signals to and from the array interior and the opposite edge of the chip.

Figure 8b. B-Type I/O Logic

2-9

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