Features |
|
|
|
|
|
|
|
|
|
|
||
∙ Single Supply for Read and Write: 2.7V to 3.6V (BV), 3.0V to 3.6V (LV) |
|
|||||||||||
∙ |
Fast Read Access Time - 120 ns |
|
|
|
|
|
||||||
∙ |
Internal Program Control and Timer |
|
|
|
|
|
||||||
∙ |
16K bytes Boot Block With Lockout |
|
|
|
|
|
||||||
∙ |
Fast Erase Cycle Time - 10 seconds |
|
|
|
|
|
||||||
∙ |
Byte-By-Byte Programming - 30 μs/Byte Typical |
|
|
|
|
|
||||||
∙ |
Hardware Data Protection |
|
|
|
|
|
|
|||||
∙ |
DATA Polling For End Of Program Detection |
|
|
|
|
|
||||||
∙ |
Low Power Dissipation |
|
|
|
|
|
8-Megabit |
|||||
|
- 25 mA Active Current |
|
|
|
|
|
||||||
∙ |
- 50 μA CMOS Standby Current |
|
|
|
|
(1M x 8) |
||||||
Typical 10,000 Write Cycles |
|
|
|
|
||||||||
∙ |
Small Packaging |
|
|
|
|
|
|
|
|
Single 2.7-volt |
||
|
- 8 x 14 mm CBGA |
|
|
|
|
|
|
|||||
Description |
|
|
|
|
|
|
|
|
Battery-Voltage™ |
|||
The AT49BV/LV080 are 3-volt-only in-system Flash Memory devices. Their 8 mega- |
Flash Memory |
|||||||||||
bits of memory are organized as 1,024,576 words by 8 bits. Manufactured with At- |
||||||||||||
mel’s advanced nonvolatile CMOS technology, the devices offer access times to 120 |
|
|||||||||||
ns with power dissipation of just 90 mW over the commercial temperature range. |
|
|||||||||||
When the device is deselected, the CMOS standby current is less than 50 μA. |
AT49BV080 |
|||||||||||
The device contains a user-enabled "boot block" protection feature. Two versions of |
||||||||||||
the feature are available: the AT49BV/LV080 locates the boot block at lowest order |
AT49BV080T |
|||||||||||
addresses ("bottom boot"); the AT49BVLV080T locates it at highest order addresses |
||||||||||||
("top boot"). |
|
|
|
|
|
|
TSOP Top View |
(continued) |
AT49LV080 |
|||
|
|
|
|
|
|
|
|
|||||
Pin Configurations |
|
|
||||||||||
|
|
Type 1 |
|
AT49LV080T |
||||||||
Pin Name |
Function |
|
|
|
|
|
|
|
||||
A0 - A19 |
Addresses |
|
|
|
|
|
|
|
||||
CE |
Chip Enable |
|
|
|
|
|
|
|
||||
OE |
Output Enable |
|
|
|
|
|
|
|||||
WE |
Write Enable |
|
|
|
|
|
|
|
||||
RESET |
Reset |
|
|
|
|
|
|
|
|
|
||
RDY/BUSY |
Ready/Busy Output |
|
|
|
|
|
||||||
I/O0 - I/O7 |
Data Inputs/Outputs |
|
|
|
|
|
||||||
|
|
CBGA Top View |
|
|
|
SOIC |
|
|
||||
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
NC |
1 |
44 |
VCC |
|
|
|
|
|
|
|
|
|
RESET |
2 |
43 |
CE |
|
|
|
|
|
|
|
|
|
A11 |
3 |
42 |
A12 |
|
|
|
|
|
|
|
|
|
A10 |
4 |
41 |
A13 |
|
|
|
|
|
|
|
|
|
A9 |
5 |
40 |
A14 |
|
|
A |
|
|
|
|
|
|
A8 |
6 |
39 |
A15 |
|
|
A5 |
A8 |
A11 |
NC |
A12 |
A15 |
A17 |
A7 |
7 |
38 |
A16 |
|
|
B |
A7 |
A10 VCC |
A13 |
NC |
A18 |
A6 |
8 |
37 |
A17 |
|
|
|
A4 |
A5 |
9 |
36 |
A18 |
|
||||||
|
C |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
A4 |
10 |
35 |
A19 |
|
|
|
A6 |
A9 |
RST |
CE |
A14 |
A16 A19 |
|
|||||
|
NC |
11 |
34 |
NC |
|
|||||||
|
D |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
NC |
12 |
33 |
NC |
|
|
|
A3 |
I/O1 |
NC VCC I/O4 |
I/O7 |
NC |
|
||||||
|
A3 |
13 |
32 |
NC |
|
|||||||
|
E |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
A2 |
14 |
31 |
NC |
|
|
|
A2 |
A0 |
I/O3 GND I/O6 |
OE |
NC |
|
||||||
|
F |
|
|
|
|
|
|
A1 |
15 |
30 |
WE |
|
|
A1 |
I/O0 |
I/O2 GND I/O5 RY/BY WE |
A0 |
16 |
29 |
OE |
|
||||
|
|
|
|
|
|
|
|
I/O0 |
17 |
28 |
RDY/BUSY |
|
|
|
|
|
|
|
|
|
I/O1 |
18 |
27 |
I/O7 |
|
|
|
|
|
|
|
|
|
I/O2 |
19 |
26 |
I/O6 |
|
|
|
|
|
|
|
|
|
I/O3 |
20 |
25 |
I/O5 |
|
|
|
|
|
|
|
|
|
GND |
21 |
24 |
I/O4 |
|
|
|
|
|
|
|
|
|
GND |
22 |
23 |
VCC |
|
|
|
|
|
|
|
|
|
|
|
|
|
0812A–8/97 |
Description (Continued)
To allow for simple in-system reprogrammability, the AT49BV/LV080 does not require high input voltages for programming. 3-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV080 is performed by erasing the entire 8 megabits of memory and then programming on a byte-by-byte basis. The typical byte programming time is a fast 30 μs. The end of a program cycle can be optionally detected by the DATA polling feature. Once
the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.
The optional 16K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
VCC |
|
|
|
|
|
|
|
|
GND |
|
|
|
|
|
|
|
|
OE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
WE |
OE, CE, AND WE |
|
||||||
|
|
|
LOGIC |
|
||||
CE |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Y DECODER |
|
|||||
ADDRESS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INPUTS |
|
X DECODER |
|
|||||
|
|
|||||||
|
|
|
|
|
|
|
|
|
Device Operation
AT49BV/LV080 |
AT49BV/LV080T |
|||
DATA INPUTS/OUTPUTS |
DATA INPUTS/OUTPUTS |
|||
I/O7 - I/O0 |
I/O7 - I/O0 |
|||
8 |
|
8 |
|
|
|
|
|
|
|
DATA LATCH |
|
DATA LATCH |
|
|
|
|
|
|
|
INPUT/OUTPUT |
|
INPUT/OUTPUT |
|
|
BUFFERS |
|
BUFFERS |
|
|
|
|
|
|
|
Y-GATING |
FFFFFH |
Y-GATING |
FFFFFH |
|
|
|
|||
MAIN MEMORY |
OPTIONAL BOOT |
|||
|
|
|||
(1008K BYTES) |
03FFFH |
BLOCK (16K BYTES) |
FC000H |
|
OPTIONAL BOOT |
MAIN MEMORY |
|||
|
|
|||
BLOCK (16K BYTES) |
00000H |
(1008K BYTES) |
00000H |
|
|
|
|||
|
|
READ: The AT49BV/LV080 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dualline control gives designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the 1024K bytes memory array (or 1008K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).
After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the in-
ternal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.
The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the AT49BV/LV080 boot block is 00000H to 03FFFH while the address range of the AT49BV/LV080T boot block is FC000H to FFFFFH.
To activate the lockout feature, a series of six program commands to specific addresses with specific data must
2 AT49BV/LV080
Device Operation (Continued)
be performed. Please refer to the Command Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation.
BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 + 0.5 volts. By doing this, protected boot block data can be altered through a chip erase, or byte programming. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active.
PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.
For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT49BV/LV080 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.
TOGGLE BIT: I n a d d i t i o n t o DATA polling, the AT49BV/LV080 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and
AT49BV/LV080
zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.
RDY/BUSY: An open drain READY/BUSY output pin provides another method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low during the internal program and erase cycles and is released at the completion of the cycle. The open drain connection allows for OR - tying of several devices to the same RDY/BUSY line.
RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be successfully completed, and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V + 0.5V input signal to the RESET pin the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section).
HARDWARE DATA PROTECTION: Hardware features p r o t e c t a g a i n s t i n a d v e r t e n t p r o g r a m s t o t h e AT49BV/LV080 in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhib- ited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.
3
Command Definition (in Hex)
Command |
Bus |
1st Bus |
2nd Bus |
3rd Bus |
4th Bus |
5th Bus |
6th Bus |
|||||||
Sequence |
Cycles |
Cycle |
Cycle |
Cycle |
Cycle |
Cycle |
Cycle |
|||||||
|
|
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
Addr |
Data |
|
Read |
1 |
Addr |
DOUT |
|
|
|
|
|
|
|
|
|
|
|
Chip Erase |
6 |
5555 |
AA |
2AAA |
55 |
5555 |
80 |
5555 |
AA |
2AAA |
55 |
5555 |
10 |
|
Byte |
4 |
5555 |
AA |
2AAA |
55 |
5555 |
A0 |
Addr |
DIN |
|
|
|
|
|
Program |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Boot Block |
6 |
5555 |
AA |
2AAA |
55 |
5555 |
80 |
5555 |
AA |
2AAA |
55 |
5555 |
40 |
|
Lockout (1) |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Product ID |
3 |
5555 |
AA |
2AAA |
55 |
5555 |
90 |
|
|
|
|
|
|
|
Entry |
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Product ID |
3 |
5555 |
AA |
2AAA |
55 |
5555 |
F0 |
|
|
|
|
|
|
|
Exit (2) |
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Product ID |
1 |
XXXX |
F0 |
|
|
|
|
|
|
|
|
|
|
|
Exit (2) |
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes: 1. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV080 and FC000H to FFFFFH for the AT49BV/LV080T.
2. Either one of the Product ID Exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias |
................. -55°C to +125°C |
||
Storage Temperature...................... |
-65°C to +150°C |
||
All Input Voltages |
|
||
(including NC Pins) |
|
||
with Respect to Ground ................... |
-0.6V to +6.25V |
||
All Output Voltages |
|
||
with Respect to Ground ............. |
- 0.6V to VCC + 0.6V |
||
|
|
|
|
Voltage on OE |
|
||
with Respect to Ground ................... |
-0.6V to +13.5V |
||
|
|
|
|
*NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
4 AT49BV/LV080