ATMEL AT49LV020-90JC, AT49LV020-70VI, AT49LV020-70VC, AT49LV020-70TI, AT49LV020-70TC Datasheet

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ATMEL AT49LV020-90JC, AT49LV020-70VI, AT49LV020-70VC, AT49LV020-70TI, AT49LV020-70TC Datasheet

Features

Single Supply Voltage, Range 2.7V to 3.6V

Single Supply for Read and Write

Fast Read Access Time - 70 ns

Internal Program Control and Timer

8K bytes Boot Block With Lockout

Fast Erase Cycle Time - 10 seconds

Byte By Byte Programming - 30 μs/Byte typical

Hardware Data Protection

DATA Polling For End Of Program Detection

Low Power Dissipation

25 mA Active Current

50 μA CMOS Standby Current

Typical 10,000 Write Cycles

Description

The AT49BV020 and the AT49LV020 are 3-volt-only, 2 megabit Flash memories organized as 262,144 words of 8 bits each. Manufactured with Atmel's advanced nonvolatile CMOS technology, the devices offer access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 μA.

To allow for simple in-system reprogrammability, the AT49BV/LV020 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV020 is performed by erasing the entire 2 megabits of memory and then programming on a byte by byte basis. The typical byte programming time is a fast 30 μs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

Pin Configuration

(continued)

 

 

 

 

 

 

Pin Name

Function

 

 

 

 

 

 

A0 - A17

Addresses

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

Write Enable

 

 

WE

 

 

 

 

 

 

I/O0 - I/O7

Data Inputs/Outputs

 

 

 

 

 

 

NC

No Connect

 

 

 

 

 

 

 

 

PLCC Top View

VSOP Top View (8 x 14mm) or

TSOP Top View (8 x 20mm)

Type 1

2-Megabit

(256K x 8)

Single 2.7-volt

Battery-Voltage

Flash Memory

AT49BV020

AT49LV020

Rev. 0678C–03/98

1

The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.

Block Diagram

Device Operation

READ: The AT49BV/LV020 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

ERASURE: Before a byte can be reprogrammed, the 256K bytes memory array (or 248K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased.

BYTE PROGRAMMING: Once the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle

time. The DATA polling feature may also be used to indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block's usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH.

Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table.

BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It

2

AT49BV020

 

 

 

AT49BV020

may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product.

For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes.

DATA POLLING: The AT49BV/LV020 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle.

T O G G L E B I T : In a d di t i on t o DATA p o l l i ng t he AT49BV/LV020 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the

device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49BV/LV020 in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle.

INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V.

Command Definition (In Hex)

 

 

1st Bus

2nd Bus

3rd Bus

4th Bus

5th Bus

6th Bus

Command

Bus

Cycle

Cycle

Cycle

Cycle

Cycle

Cycle

 

 

 

 

 

 

 

 

 

 

 

 

Sequence

Cycles

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

Addr

Data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

1

Addr

DOUT

 

 

 

 

 

 

 

 

 

 

Chip Erase

6

5555

AA

2AAA

55

5555

80

5555

AA

2AAA

55

5555

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Program

4

5555

AA

2AAA

55

5555

A0

Addr

DIN

 

 

 

 

Boot Block

6

5555

AA

2AAA

55

5555

80

5555

AA

2AAA

55

5555

40

Lockout(1)

 

 

 

 

 

 

 

 

 

 

 

 

 

Product ID Entry

3

5555

AA

2AAA

55

5555

90

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Product ID Exit(2)

3

5555

AA

2AAA

55

5555

F0

 

 

 

 

 

 

Product ID Exit(2)

1

XXXX

F0

 

 

 

 

 

 

 

 

 

 

Notes: 1. The 8K byte boot sector has the address range of 00000H to 01FFFH.

2. Either one of the Product ID exit commands can be used.

Absolute Maximum Ratings*

Temperature Under Bias

................................ -55°C to +125°C

*NOTICE: Stresses beyond those listed under “Absolute

 

 

 

 

Maximum Ratings” may cause permanent dam-

Storage Temperature .....................................

-65°C to +150°C

age to the device. This is a stress rating only and

 

 

 

 

functional operation of the device at these or any

All Input Voltages

 

other conditions beyond those indicated in the

(including NC Pins)

 

operational sections of this specification is not

with Respect to Ground ...................................

-0.6V to +6.25V

implied. Exposure to absolute maximum rating

All Output Voltages

 

conditions for extended periods may affect device

- 0.6V to VCC + 0.6V

reliability.

with Respect to Ground .............................

 

Voltage on

 

 

 

 

OE

 

 

with Respect to Ground ...................................

-0.6V to +13.5V

 

 

 

 

 

 

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