ATMEL AT45DB161-TI, AT45DB161-TC, AT45DB161-RI, AT45DB161-RC, AT45DB161-JI Datasheet

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16-Megabit
2.7-volt Only
Serial
DataFlash
®
AT45DB161
Preliminary
Single 2.7V - 3.6V Supply
Serial Interface Arch itec ture
Page Program Operation
Single Cycle Reprogram (Erase and Program)
4096 Pages (528 Bytes/Page) Main Memory
Optional Page and Block Erase Operations
Two 528-Byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
Internal Program and Control Timer
Fast Page Program Time – 7 ms Typical
120
µ
µµ
µ
s Typical Page to Buffer Transfer Time
Low Power Dissipation
4 mA Active Read Current Typical
–3
µ
µµ
µ
A CMOS Standby Current Typical
13 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT45DB161 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 17,301,504 bits of memory are organized as 4096 pages of
528 bytes each. In addition to the main me mory, the AT45DB1 61 also contai ns two
SRAM data buffers of 528 bytes each. The buffers allow receiving of data while a
page in the main memory is being reprogrammed. Unlike conventional Flash memo-
Rev. 0807C–07/98
Pin Configurations
Pin Name Function
CS
Chip Select
SCK Serial Clock
SI Serial Input
SO Serial Output
WP
Hardware Page
Write Protect Pin
RESET
Chip Reset
RDY/BUSY
Ready/Busy
(continued)
TSOP Top View
Ty pe 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PLCC
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
SCK
SI
SO
NC
NC
NC
NC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
4
3
2
1
32
31
30
14
15
16
17
18
19
20
NC
NC
DC
DC
NC
NC
NC
CS
NC
NC
GND
VCC
NC
NC
SOIC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
NC
NC
CS
SCK
SI
SO
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
WP
RESET
RDY/BUSY
NC
NC
NC
NC
NC
NC
NC
NC
CBGA Top View
Through Package
A
B
C
D
E
1
2345
NC
NC
NC
NC
NC
VCC
WP
RESET
NC
NC
GND
RDY/BSY
SI
NC
NC
SCK
CS
SO
NC
NC
NC
NC
NC
NC
Note: PLCC package pins 16
and 17 are DON’T CONNECT
AT45DB161
Preliminary 16-
Megabit 2.7-volt
Only Serial
DataFlash
AT45DB161
2
ries that are accessed randomly with multiple address lines
and a parallel interface, the DataFlash uses a seri al inter-
face to sequentially access its data. The simple serial inter-
face facilitates hardware layout, increases system
reliability, minim ize s switching noise, and r edu ce s pa ck ag e
size and active pin count. The device is optimized for use in
many commercial and industr ial applications where hig h
density, low pin coun t, low voltage, and lo w power are
essential. Typical applications for the DataFlash are digital
voice storage, image storage, and data storage. The
device operates at clock freque ncies up to 1 3 MHz with a
typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the
AT45DB161 does not require high input voltages for pro-
gramming. The devi ce operate s from a s ingle po wer sup-
ply, 2.7V to 3.6V, for both the program and read
operations. The AT45DB161 is enabled through the chip
select pin (CS
) and accessed via a three-wire interface
consisting of the Serial Input (SI), Serial Output (SO), and
the Serial Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
Memory Array
To provide optimal flexibility, the memory array of the
AT45DB161 is di vide d into th ree lev els of gr anula rity co m-
prising of sectors, bl ocks, and page s. The Memory Arch i-
tecture Diagram illustrates the breakdown of each level and
details the number of pages per sector and block. All pr o-
gram operations to the DataFlash occur on a page by page
basis; however, the optional erase operations can be per-
formed at the block or page level.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)BUFFER 1 (528 BYTES)
I/O INTERFACE
SCK
CS
RESET
V
CC
GND
RDY/BUSY
WP
SOSI
AT45DB161
3
Memory Architecture Diagram
Device Operation
The device operation is controlled by instructions from the
host processor. The l is t o f in st ru cti on s a nd thei r as so ci ated
opcodes are contained in T able 1 and Table 2. A valid
instruction starts with the falling edge of CS
followed by the
appropriate 8-bit opcode and the desired buffer or main
memory address loc ati on. Whi le the CS
pin is low, toggl in g
the SCK pin controls the loading of the opcode and the
desired buffer or main memory address location through
the SI (serial input) pin. All instructions, addresses, and
data are transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ:
A main memory read allows
the user to read data directly from any one of the 4096
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits . In the AT45DB 161, the
first two address bits are reserved for l arger density
devices (see Notes on page 10), the nex t 12 address bi ts
(PA11-PA0) specify the page address, and the next 10
address bits (BA9-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS
pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same pag e. A l ow to hig h trans i tion on th e
CS
pin will terminate the read operation and tri-state the
SO pin.
BUFFER READ:
Data can be re ad from ei ther one of the
two buffers, usin g di fferen t o pc ode s to s pe cify wh ic h bu ffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
buffer 2. To perfo rm a buffer read, the eight bits o f the
opcode must b e follow ed b y 14 don’ t ca re b its, 10 a ddre ss
bits, and eight don't care bits. Since the buffer size is 528-
bytes, 10 address bits (BFA9-BFA0) are required to specify
the first byte of data to be read from the buffer. The CS
pin
must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data.
When the end of a buffer is reached, the device will con-
tinue reading back at the beginning of the buffer. A low to
Sector = 135,168 bytes
(128K + 4K)
32 Blocks
(256 Pages)
SECTOR 0
SECTOR 1
SECTOR 2
SECTOR 3
SECTOR 4
SECTOR 5
SECTOR 6
SECTOR 7
SECTOR 8
SECTOR 9
SECTOR 10
SECTOR 11
SECTOR 12
SECTOR 13
SECTOR 14
SECTOR 15
Block = 4224 bytes
(4K + 128)
8 Pages
BLOCK 0
BLOCK 1
BLOCK 30
BLOCK 31
BLOCK 32
BLOCK 33
BLOCK 510
BLOCK 511
SECTOR 0
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 66
BLOCK 509
SECTOR 1
Page = 528 bytes
(512 + 16)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 4094
PAGE 4095
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 4093
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
AT45DB161
4
high transition o n the CS
pin will termina te th e re ad op era-
tion and tri-state the SO pin.
MAIN MEMORY PAGE TO BUFFER TRANSFER:
A page
of data can be transferred from the main memory to either
buffer 1 or buffer 2. An 8-bit opcode, 53H for buffer 1 and
55H for buffer 2, is followed by the two reserved bits, 12
address bits (PA11-PA0) which specify the page in main
memory that is to be transfe rred, and 10 don’t care bits.
The CS
pin must be low while to ggling the SCK pin to loa d
the opcode, the address bit s, and the don ’t care bits from
the SI pin. The transfer of the page of data from the main
memory to the buffer will begin when the CS
pin transitions
from a low to a high state. During the transfer of a page of
data (t
XFR
), the status register can be read to determin e
whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE:
A page of
data in main memory can be compared to the data in buffer
1 or buffer 2. An 8-bit opcode , 60 H for bu ffer 1 and 61H for
buffer 2, is followed by 24 address bits consisting of the two
reserved bits, 12 address bits (PA11-PA0) which specify
the page in the main memory that is to be compar ed to the
buffer, and 10 don't care bits. The loading of the opcode
and the address bits is the same as described previously.
The CS
pin must be low while to ggling the SCK pin to loa d
the opcode, the address bits, and the don't care bits from
the SI pin. On the low to high transi tion of the CS
pin, the
528 bytes in the selected main memory page will be com-
pared with the 528 b ytes in buf fer 1 or buffe r 2. During th is
time (t
XFR
), the status register will indicate that the part is
busy. On co mplet ion o f t he co mpar e op era tion, bit 6 o f th e
status register is updated with the result of the compare.
Program
BUFFER WRITE:
Data can be shif ted in from the SI pi n
into either buffer 1 or bu ffer 2. To load data into ei ther
buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2,
is followed by 14 don't care bits and 10 address bits (BFA9-
BFA0). The 10 address bits specify the first by te in the
buffer to be written. The data is entered follow ing the
address bits. If the end of the data buffer is reached, the
device will wrap around back to the beginning of the buffer.
Data will continue to be l oaded i nto the b uffer unti l a low t o
high transition is detected on the CS
pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH
BUILT-IN ERASE:
Data written into either buff er 1 or bu ffer
2 can be programmed into the main memory. An 8-bit
opcode, 83H for buf fer 1 o r 86 H for buff er 2, is f ollow ed by
the two reserved bits, 12 address bits (PA11-PA 0) that
specify the p age in the main memor y to be writ ten, an d 10
additional don't care bits. When a low to high transition
occurs on the CS
pin, the part will first erase the selec ted
page in main memory to all 1s and then program the data
stored in the buffer in to the specified page i n the main
memory. Both th e erase an d the pro grammi ng of the p age
are internally self timed and should take place in a maxi-
mum time of t
EP
. During this time, the status register will
indicate that the part is busy.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH-
OUT BUILT-IN ERASE:
A previously erased page within
main memory can be p rogrammed with the conten ts of
either buffer 1 or buffer 2. An 8-bit opcode, 88H for buffer 1
or 89H for buffer 2, is fol lowed by th e two re served bits, 1 2
address bits (PA11-PA0) that specify the page in the main
memory to be written, and 10 additional don’t care bits.
When a low to high transition occurs on the CS
pin, the part
will program the data stored in the buffer into the specified
page in the main memory. It is necessary that the page in
main memory that is being programmed has been previ-
ously erased. The programmi ng of the page is internally
self timed and should take place in a maximum time of t
P
.
During this time, the status register w ill indicate that th e
part is busy.
PAGE ERASE:
The optional Page Erase comma nd can b e
used to individually er ase any page in the main memory
array allowing the Buffer to Main Memory Page Program
without Built-In Erase command to be utilized at a later
time. To perform a P age E rase , an op co de of 8 1H must be
loaded into the device, followed by two reserved bits, 12
address bits (PA11-PA0), and 10 don’t care bits. The 12
address bits are used to specify whi ch page of the memo ry
array is to be erased. Wh en a low to hig h transiti on occu rs
on the CS
pin, the part will erase the selected page to 1s.
The erase operation is internally self-timed and should take
place in a maximum time of t
PE
. During this time, the status
register will indicate that the part is busy.
BLOCK ERASE:
A block of eight pages can be erased at
one time allowing the Buffer to Main Me mory Page Pro-
gram without Built-In Erase command to be utilized to
reduce programming times when writing large amounts of
data to the device. To perform a Block Erase, an opcode of
50H must be loaded into the device, followed by two
reserved bits, nine address bits (PA11-PA3), and 13 don’t
care bits. The nine address bits are used to specify which
block of eight pages is to be erased. When a low to high
transition occurs on the CS
pin, the part will erase the
selected block o f eigh t pages to 1s. The er ase oper ation is
internally self -timed an d should tak e place in a max imum
time of t
BE
. During this time, the stat us re giste r will in dica te
that the part is busy.
AT45DB161
5
MAIN MEMORY PAGE PROGRAM:
This operation is a
combination of the Buffer Write and Buffer to Main Memory
Page Program with Built-In Erase ope rations. Data is first
shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. An 8-
bit opcode, 82H f or b uffer 1 or 85H for b uffer 2, i s foll owed
by the two reserve d bits an d 22 addre ss bit s. The 12 mo st
significant address bits (PA11-PA0) select the page in the
main memory where data is to be written, and the next 10
address bits (BFA 9-BFA0) se lect the fi rst by te i n the buffer
to be written. After all address bi ts are shifted in, the part
will take data from the SI pin and store it in one of the data
buffers. If the end of the b uffer i s reached , the de vice will
wrap around back to the beginning of the buffer. Wh en
there is a low to high transition on the CS
pin, the part will
first erase the selected page in main memory to all 1s and
then program the data stored in the buffer into the specified
page in the main memory. Both the erase and the program-
ming of the page are internally self timed and should take
place in a maximum of time t
EP
. During this time, the status
register will indicate that the part is busy.
AUTO PAGE REWRITE:
This mode is only needed if multi-
ple bytes within a page or mu ltiple pag es of data are mod i-
fied in a random fashion. This mode is a combination of two
operations : Main Mem ory Page to B uffer Tran sfer and
Buffer to Main Memory Page Program with Built-In Erase.
A page of data is first transf erred fr om the main me mory to
buffer 1 or buffer 2, and then the same data (from buffer 1
or buffer 2) is p rogrammed bac k into its original pag e of
main memory. An 8- bit op code, 5 8H for buffer 1 or 59H for
buffer 2, is followed by the two reserved bits, 12 address
bits (PA11-PA0) tha t specify the page in mai n memory to
be rewritten, and 10 additional don't care bits. When a low
to high transition occurs on the CS
pin, the part will first
transfer data from the page in main memory to a buffer and
then program the data from the buffer back into same page
of main memor y. The ope ratio n is intern ally self-ti med an d
should take place in a maximum time of t
EP
. During this
time, the status register will indicate that the part is busy.
If a sector is programmed or reprogrammed sequentially
page by page, then the programming algorithm shown in
Figure 1 is recomm ended. Other wise, if mu ltipl e bytes in a
page or several pa ges are p r ogr am med rando ml y i n a se c-
tor, then the progr amming alg orithm sh own in Figur e 2 is
recommended.
STATUS REGISTER:
The status register can be used to
determine the device’s ready/busy status, the result of a
Main Memory Page to Buffer Compa re operation, or the
device density. To read the status register, an opcode of
57H must be loaded in to th e d ev ice. A fte r the las t b it of th e
opcode is shifted in, the eig ht bits of the status register,
starting with the MSB (bit 7), will be shifted out on the SO
pin during the next eight clock cycles. The five most-signifi-
cant bits of the status register will contain device infor ma-
tion, while the remaining three least-significant bits are
reserved for future use and will have undefined values.
After bit 0 of the status register has been shifted out, the
sequence will repeat itse lf (as long as CS
remains lo w an d
SCK is being toggled ) startin g again wit h bit 7. The data in
the status register is constantly updated, so each repeating
sequence will output new data.
Ready/busy status is indicated using bit 7 of the status reg-
ister. If bit 7 is a 1, th en the device is not bus y and is re ady
to accept the next comman d. If bit 7 i s a 0, then the devic e
is in a busy state. The user can continuously poll bit 7 of the
status register by stopping SCK once bit 7 has been output.
The status of bit 7 will continue to b e o utp ut o n the SO pin,
and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can
Block Erase Addressing
PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
000000000XXX0
000000001XXX1
000000010XXX2
000000011XXX3
111111100XXX508
111111101XXX509
111111110XXX510
111111111XXX511
AT45DB161
6
cause the device to be in a busy s ta te: Main Memory Pag e
to Buffer Transfer, Main Memory Page to Buffer Compare,
Buffer to Main Memory Page Program with Built-In Erase,
Buffer to Main Memory Page Program without Built-In
Erase, Page Erase, Block Erase, Main Memory Page Pro-
gram, and Auto Page Rewrite.
The result of the mos t recent Ma in Memor y Page to B uffer
Compare opera tion is indic ated using bi t 6 of the status
register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at
least one bit of the data in the main memory page does not
match the data in the buffer.
The device density is indicate d using bits 5, 4, and 3 of the
status register. For the AT45 DB1 61, t he th re e bi ts ar e 1, 0 ,
and 1. The decimal value of these three binary bits does
not equate to th e dev ice d ensi ty; th e thr ee b its re presen t a
combinational code r elating to di ffering den sities of Ser ial
DataFlash devices, allowing a total of eight different density
configurations.
Read/Program Mode Summary
The modes lis ted abo ve can be sepa rated into tw o grou ps
— modes which make use of the flash memory array
(Group A) and modes which do not make use of the flas h
memory array (Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program With
Built-In Erase
5. Buffer 1 (or 2) to Main Memory Page Program With-
out Built-In Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in pro gress ( not full y comple ted) the n
another mode in Group A should not be started. However,
during this time in which a Group A mode is in progress,
modes in Group B can be started.
This gives the S erial DataFlash the ability to virtua lly
accommodate a co ntinuous data stre am. While data is
being programmed into main memory from buffer 1, data
can be loaded into buff er 2 (o r vice v ersa) . See applica tio n
note AN-4 (“Using Atmel’s Serial DataFlash”) for more
details.
HARDWARE PAGE WRITE PROTECT:
If the WP
pin is
held low, the first 256 pages of the main memory cannot be
reprogrammed. The only way to reprogram the first 256
pages is to first dri ve the prot ect pin high and then us e the
program commands previously mentioned. The WP
pin is
internally pulled high; therefore, connection of the WP
pin is
not necessary if this pin and feature will not be utilized.
However, it is recommended that the WP
pin be driven high
externally whenever possible.
RESET
:
A low state on the re set pin (RESE T
) will terminate
the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset
condition as long as a low level is pr esent on the RESE T
pin. Normal operation can resume once the RESET pin is
brought back to a high level.
The device incorporates an internal power-on reset circuit,
so there are no restrictions on the RESET
pin during
power-on sequences. The RESET
pin is also internally
pulled high; therefore, connection of the RESET
pin is not
necessary if this pin and fea ture will not be utili zed. How-
ever, it is recommended that the RESE T
pin be driven high
externally whenever possible.
READY/BUSY
:
This open dra in output pin will be dri ven
low when the device is busy in an internally self-timed oper-
ation. This pin, which is normally in a high state (through an
external pull-up resistor), will be pulled low during program-
ming operations, compare operations, and during page-to-
buffer transfers.
The busy status indic at es that the Flas h m emo ry a rray an d
one of the buffers cannot be accessed; read and write
operations to the other buffer can still be performed.
Power On/Reset State
When power is first applied to the device, o r w hen re co ve r-
ing from a reset conditio n, the device will defau lt to SPI
mode 3. In addition, the SO pin will be in a high im peda nc e
state, and a high to low transition on the CS
pin will be
required to start a valid instruction. The SPI mode will be
automatically select ed on ever y falling ed ge of CS
by sam-
pling the inactive clock state.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY
COMP101XXX
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